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[209.85.128.41]) by smtp.gmail.com with ESMTPSA id s1sm3372825ejx.25.2021.01.08.01.54.54 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 Jan 2021 01:54:54 -0800 (PST) Received: by mail-wm1-f41.google.com with SMTP id n16so6400653wmc.0 for ; Fri, 08 Jan 2021 01:54:54 -0800 (PST) X-Received: by 2002:a7b:c92b:: with SMTP id h11mr2296894wml.99.1610099693765; Fri, 08 Jan 2021 01:54:53 -0800 (PST) MIME-Version: 1.0 References: <20201209080102.26626-1-yong.wu@mediatek.com> <1609239977.26323.292.camel@mhfsdcap03> In-Reply-To: <1609239977.26323.292.camel@mhfsdcap03> From: Tomasz Figa Date: Fri, 8 Jan 2021 18:54:41 +0900 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v5 18/27] iommu/mediatek: Add power-domain operation To: Yong Wu Cc: Joerg Roedel , Matthias Brugger , Rob Herring , Will Deacon , Robin Murphy , youlin.pei@mediatek.com, linux-devicetree , Nicolas Boichat , srv_heupstream , chao.hao@mediatek.com, Linux Kernel Mailing List , Evan Green , "list@263.net:IOMMU DRIVERS , Joerg Roedel ," , "moderated list:ARM/Mediatek SoC support" , Krzysztof Kozlowski , anan.sun@mediatek.com, "list@263.net:IOMMU DRIVERS , Joerg Roedel ," Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, Dec 29, 2020 at 8:06 PM Yong Wu wrote: > > On Wed, 2020-12-23 at 17:36 +0900, Tomasz Figa wrote: > > On Wed, Dec 09, 2020 at 04:00:53PM +0800, Yong Wu wrote: > > > In the previous SoC, the M4U HW is in the EMI power domain which is > > > always on. the latest M4U is in the display power domain which may be > > > turned on/off, thus we have to add pm_runtime interface for it. > > > > > > When the engine work, the engine always enable the power and clocks for > > > smi-larb/smi-common, then the M4U's power will always be powered on > > > automatically via the device link with smi-common. > > > > > > Note: we don't enable the M4U power in iommu_map/unmap for tlb flush. > > > If its power already is on, of course it is ok. if the power is off, > > > the main tlb will be reset while M4U power on, thus the tlb flush while > > > m4u power off is unnecessary, just skip it. > > > > > > There will be one case that pm runctime status is not expected when tlb > > > flush. After boot, the display may call dma_alloc_attrs before it call > > > pm_runtime_get(disp-dev), then the m4u's pm status is not active inside > > > the dma_alloc_attrs. Since it only happens after boot, the tlb is clean > > > at that time, I also think this is ok. > > > > > > Signed-off-by: Yong Wu > > > --- > > > drivers/iommu/mtk_iommu.c | 41 +++++++++++++++++++++++++++++++++------ > > > 1 file changed, 35 insertions(+), 6 deletions(-) > > > > > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > > > index 6fe3ee2b2bf5..0e9c03cbab32 100644 > > > --- a/drivers/iommu/mtk_iommu.c > > > +++ b/drivers/iommu/mtk_iommu.c > > > @@ -184,6 +184,8 @@ static void mtk_iommu_tlb_flush_all(void *cookie) > > > struct mtk_iommu_data *data = cookie; > > > > > > for_each_m4u(data) { > > > + if (!pm_runtime_active(data->dev)) > > > + continue; > > > > Is it guaranteed that the status is active in the check above, but then > > the process is preempted and it goes down here? > > > > Shouldn't we do something like below? > > > > ret = pm_runtime_get_if_active(); > > if (!ret) > > continue; > > if (ret < 0) > > // handle error > > > > // Flush > > > > pm_runtime_put(); > > Make sense. Thanks. There is a comment in arm_smmu.c "avoid touching > dev->power.lock in fastpaths". To avoid this here too(we have many SoC > don't have power-domain). then the code will be like: > > bool has_pm = !!data->dev->pm_domain; > > if (has_pm) { > if (pm_runtime_get_if_in_use(data->dev) <= 0) > continue; > } > > xxxx > > if (has_pm) > pm_runtime_put(data->dev); Looks good to me, thanks. > > > > Similar comment to the other places being changed by this patch. > > > > > writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, > > > data->base + data->plat_data->inv_sel_reg); > > > writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); > > > @@ -200,6 +202,10 @@ static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, > > > u32 tmp; > > > > > > for_each_m4u(data) { > > > + /* skip tlb flush when pm is not active. */ > > > + if (!pm_runtime_active(data->dev)) > > > + continue; > > > + > > > spin_lock_irqsave(&data->tlb_lock, flags); > > > writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, > > > data->base + data->plat_data->inv_sel_reg); > [snip]