From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CC92C388F9 for ; Sun, 8 Nov 2020 01:54:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2788720878 for ; Sun, 8 Nov 2020 01:54:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1604800468; bh=5N/oNzrmeu3aOtDAHcU54Nt3NGOMRnUUf8OnNnCXcWA=; h=References:In-Reply-To:From:Date:Subject:To:Cc:List-ID:From; b=YTJCfUoPaaguoshI0XczEs4kKMVh8hfFw3/TUiUWAMRPlJYKE0kgeB+zwe1v3iHfI 2IBpyPYNJGdDawu/Gk1N88dWOHWqPdQUNHDYRclY+PKaDFM5/+vXwamOlonxvmj93U 6dkBEfqKS1UblYmONXNhOysUhxBGNlr79AfuBwFE= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727871AbgKHBy1 (ORCPT ); Sat, 7 Nov 2020 20:54:27 -0500 Received: from mail.kernel.org ([198.145.29.99]:53094 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727432AbgKHBy1 (ORCPT ); Sat, 7 Nov 2020 20:54:27 -0500 Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 23683221FC; Sun, 8 Nov 2020 01:54:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1604800466; bh=5N/oNzrmeu3aOtDAHcU54Nt3NGOMRnUUf8OnNnCXcWA=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=YQRexxsWat85DKj1qNwAszWih5nB4XBXAT4Q8jHuBplQNSlCR7sedt8rn8EdmR2XX 8JUBFzJnb6WTa+ChRgM1m7sXKKq4zcFtaRjASABA0klqF6iWY09q6gt45UeC0zIL2c IzKLPIHYiLedvAtL6T0f4tppdwTf9CqIz0Q5bPHI= Received: by mail-ed1-f44.google.com with SMTP id cq7so4895669edb.4; Sat, 07 Nov 2020 17:54:26 -0800 (PST) X-Gm-Message-State: AOAM530Q7URi8BLE+le27P1cC+GFYd8bUyUE/3TbVKsD7+j7NqeuQ8iw TqPyxc56ILxL+d2CqgTewmp3p4eJnRhKCXkwTA== X-Google-Smtp-Source: ABdhPJz9PLvOVHmdu2y0FOkaVh+eRhblRF0PoRpr3EGHovwbntqZAc8CKlK37k+KXdox0EpoWbXJydOn5iVXuc0kGs0= X-Received: by 2002:a50:8745:: with SMTP id 5mr8862319edv.49.1604800464719; Sat, 07 Nov 2020 17:54:24 -0800 (PST) MIME-Version: 1.0 References: <20201023133130.194140-1-fparent@baylibre.com> <20201023133130.194140-4-fparent@baylibre.com> In-Reply-To: <20201023133130.194140-4-fparent@baylibre.com> From: Chun-Kuang Hu Date: Sun, 8 Nov 2020 09:54:14 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 3/5] drm/mediatek: add disp-color MT8167 support To: Fabien Parent Cc: "moderated list:ARM/Mediatek SoC support" , Linux ARM , linux-kernel , DTML , DRI Development , Matthias Brugger , Rob Herring , Daniel Vetter , David Airlie , Philipp Zabel , Chun-Kuang Hu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi, Fabien: Fabien Parent =E6=96=BC 2020=E5=B9=B410=E6=9C=8823= =E6=97=A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=889:31=E5=AF=AB=E9=81=93=EF=BC= =9A > > Add support for disp-color on MT8167 SoC. For this patch, applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/= log/?h=3Dmediatek-drm-next Regards, Chun-Kuang. > > Signed-off-by: Fabien Parent > Reviewed-by: Chun-Kuang Hu > --- > > Changelog: > > V2: No change > > drivers/gpu/drm/mediatek/mtk_disp_color.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/= mediatek/mtk_disp_color.c > index 3ae9c810845b..a1227cefbf31 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_color.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c > @@ -16,6 +16,7 @@ > > #define DISP_COLOR_CFG_MAIN 0x0400 > #define DISP_COLOR_START_MT2701 0x0f00 > +#define DISP_COLOR_START_MT8167 0x0400 > #define DISP_COLOR_START_MT8173 0x0c00 > #define DISP_COLOR_START(comp) ((comp)->data->color_offs= et) > #define DISP_COLOR_WIDTH(comp) (DISP_COLOR_START(comp) += 0x50) > @@ -148,6 +149,10 @@ static const struct mtk_disp_color_data mt2701_color= _driver_data =3D { > .color_offset =3D DISP_COLOR_START_MT2701, > }; > > +static const struct mtk_disp_color_data mt8167_color_driver_data =3D { > + .color_offset =3D DISP_COLOR_START_MT8167, > +}; > + > static const struct mtk_disp_color_data mt8173_color_driver_data =3D { > .color_offset =3D DISP_COLOR_START_MT8173, > }; > @@ -155,6 +160,8 @@ static const struct mtk_disp_color_data mt8173_color_= driver_data =3D { > static const struct of_device_id mtk_disp_color_driver_dt_match[] =3D { > { .compatible =3D "mediatek,mt2701-disp-color", > .data =3D &mt2701_color_driver_data}, > + { .compatible =3D "mediatek,mt8167-disp-color", > + .data =3D &mt8167_color_driver_data}, > { .compatible =3D "mediatek,mt8173-disp-color", > .data =3D &mt8173_color_driver_data}, > {}, > -- > 2.28.0 >