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[209.85.160.171]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4a4358d37cdsm90082971cf.40.2025.06.04.00.17.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Jun 2025 00:17:57 -0700 (PDT) Received: by mail-qt1-f171.google.com with SMTP id d75a77b69052e-4a43cbc1ab0so75531791cf.0; Wed, 04 Jun 2025 00:17:57 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCUGFEGvWT0X1eZyREBXAHHGk+1RkHPThNGKT2/dbUCeDSJluQC1fp5Exn0N3G8n2mKaZQBLXQi3dgv3@vger.kernel.org, AJvYcCWCkos9rCM/PMUTqs9s95gVLLjJ7fltJNRfdOZvHfyS0pUrU5nQYoazA9yIsKb0qp6bqBxqHu9lziVc@vger.kernel.org, AJvYcCWIPy8rQR7m0WLm3otQ2EjGkSqYXPuQW0WCmUML89Tk9RWHbCU06brEgqcHZBRSIiA/oDiEgLhorPzch/fr@vger.kernel.org, AJvYcCWrOGyzNEZd2JdUev6mUxwGsTnsVeeyhjNVEKdWW+7lUqANkOO4ZmPRSmoIn621/IGp1zcvP9gJdnIVAtM=@vger.kernel.org X-Received: by 2002:a05:6902:6c12:b0:e81:4200:e227 with SMTP id 3f1490d57ef6-e8179ef4b9amr1895455276.40.1749021096375; Wed, 04 Jun 2025 00:11:36 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250520-6-10-rocket-v5-0-18c9ca0fcb3c@tomeuvizoso.net> <20250520-6-10-rocket-v5-1-18c9ca0fcb3c@tomeuvizoso.net> In-Reply-To: From: Tomeu Vizoso Date: Wed, 4 Jun 2025 09:11:25 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: AX0GCFuzVw9QOJbPU8rAaiE__0pakSdSWD2x8uriT207nU1DMDYnxHzJRzNlcz4 Message-ID: Subject: Re: [PATCH v5 01/10] dt-bindings: npu: rockchip,rknn: Add bindings To: Rob Herring Cc: Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Oded Gabbay , Jonathan Corbet , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Sumit Semwal , =?UTF-8?Q?Christian_K=C3=B6nig?= , Sebastian Reichel , Nicolas Frattaroli , Jeff Hugo , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-doc@vger.kernel.org, linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org, Kever Yang Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, May 28, 2025 at 5:34=E2=80=AFPM Tomeu Vizoso wrote: > > On Wed, May 28, 2025 at 3:41=E2=80=AFPM Rob Herring wro= te: > > > > On Tue, May 20, 2025 at 5:27=E2=80=AFAM Tomeu Vizoso wrote: > > > > > > Add the bindings for the Neural Processing Unit IP from Rockchip. > > > > > > v2: > > > - Adapt to new node structure (one node per core, each with its own > > > IOMMU) > > > - Several misc. fixes from Sebastian Reichel > > > > > > v3: > > > - Split register block in its constituent subblocks, and only require > > > the ones that the kernel would ever use (Nicolas Frattaroli) > > > - Group supplies (Rob Herring) > > > - Explain the way in which the top core is special (Rob Herring) > > > > > > v4: > > > - Change required node name to npu@ (Rob Herring and Krzysztof Kozlow= ski) > > > - Remove unneeded items: (Krzysztof Kozlowski) > > > - Fix use of minItems/maxItems (Krzysztof Kozlowski) > > > - Add reg-names to list of required properties (Krzysztof Kozlowski) > > > - Fix example (Krzysztof Kozlowski) > > > > > > v5: > > > - Rename file to rockchip,rk3588-rknn-core.yaml (Krzysztof Kozlowski) > > > - Streamline compatible property (Krzysztof Kozlowski) > > > > > > Signed-off-by: Sebastian Reichel > > > Signed-off-by: Tomeu Vizoso > > > --- > > > .../bindings/npu/rockchip,rk3588-rknn-core.yaml | 147 +++++++++++= ++++++++++ > > > 1 file changed, 147 insertions(+) > > > > > > diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rk= nn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-c= ore.yaml > > > new file mode 100644 > > > index 0000000000000000000000000000000000000000..9eb426367afcbc03c387d= 43c4b8250cdd1b9ee86 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core= .yaml > > > @@ -0,0 +1,147 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yam= l# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Neural Processing Unit IP from Rockchip > > > + > > > +maintainers: > > > + - Tomeu Vizoso > > > + > > > +description: > > > + Rockchip IP for accelerating inference of neural networks, based o= n NVIDIA's > > > + open source NVDLA IP. > > > + > > > + There is to be a node per each core in the NPU. In Rockchip's desi= gn there > > > + will be one core that is special and needs to be powered on before= any of the > > > + other cores can be used. This special core is called the top core = and should > > > + have the compatible string that corresponds to top cores. > > > > Is this really a distinction in the h/w? If you change which core is > > the top one in the DT, does it still work? > > No, I really need to power on that one before the others can work (the > first core is also marked as special in a diagram in the TRM). > > > > + > > > +properties: > > > + $nodename: > > > + pattern: '^npu@[a-f0-9]+$' > > > + > > > + compatible: > > > + enum: > > > + - rockchip,rk3588-rknn-core-top > > > + - rockchip,rk3588-rknn-core > > > + > > > + reg: > > > + maxItems: 3 > > > + > > > + reg-names: > > > + items: > > > + - const: pc > > > + - const: cna > > > + - const: core > > > + > > > + clocks: > > > + minItems: 2 > > > + maxItems: 4 > > > + > > > + clock-names: > > > + items: > > > + - const: aclk > > > + - const: hclk > > > + - const: npu > > > + - const: pclk > > > + minItems: 2 > > > > It is odd that the non-top cores only have bus clocks and no module > > clock. But based on the clock names, I'm guessing the aclk/hclk are > > not shared, but the npu and pclk are shared. Since you make the top > > core probe first, then it will enable the shared clocks and the > > non-top cores don't have to worry about them. If so, that is wrong as > > it is letting the software design define the bindings. > > Yes, I think it's probably as you say, but I don't know how I could > check. Maybe Kever, Heiko or Sebastian would have any ideas? So I talked with Kever and Heiko about this, and the npu and pclk clocks are indeed shared among cores. Regards, Tomeu