From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1C67C433F5 for ; Wed, 18 May 2022 08:22:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232880AbiERIWh (ORCPT ); Wed, 18 May 2022 04:22:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232879AbiERIWd (ORCPT ); Wed, 18 May 2022 04:22:33 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1588E1059DE for ; Wed, 18 May 2022 01:22:30 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id r30so1520585wra.13 for ; Wed, 18 May 2022 01:22:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=trjJ+b0UjHlSF876BjNjmr4z+E9qBj2MQAPe6nMnBlA=; b=kFQL87UQWcFbmG99QsHcYpdeBr7/o0aCWLZs4cACELBQusFJkwnRf0pnFO4BDWplkx cDH2SaMQtqvmmKd7YarcDr6MKTgLipa+MYrk5MqwCbBnMNf0NtADKSO1xlrn93fWfEL/ kOPiVL45nY/gbVwf2E1xkzd1+wEqe/kxQhllGmASlFvU84YmE2Hylbv0Gk16JInDXOvT cqqGAdCBMYABt4E8pwn6a5vPq5uFMzhvZn8SBBEMtLTWXJxLINkJVYQgvss+bOHe0FgK AWYyC7JcIRMSt2qMLbJGKE/3FiNuDammjR3pelAzq11lv/7jtKbhXzmbP7fWxM5jPlte zRbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=trjJ+b0UjHlSF876BjNjmr4z+E9qBj2MQAPe6nMnBlA=; b=fjn9W+A2r8zeBcOCSh5xkFRR/509y/6ikeOpjr/9n2Rg5kbE89m054zBMHysxDyy5K 3PWBbhP+EsNUuF/YJns9VkiZ0SZ2elGG+r26YTVBJ07VNTlPvtVI2CnO6vazAwZ3qjt4 pu/KlPZ1svCJAjxPMxEotw6FNGR6m0zFVNd3lLgeUTgmDtbVZhpOzf6ILVRKBrUTpDXG EJlLklRjCDAQnbvPUTWwfcCP06CLcapJWZLQaXBQSOB0sVKSnkYQ4Be6zmDaYHNP7SOX miG6k7N0z/7aNq2QmkBkdcx0gol2cyCxTtE5NJfVx14cCyEmTmkEjo34IqpcTV6i7IHX ruAA== X-Gm-Message-State: AOAM533Ki1UIwDwsnge8dvVBE77cGA+Is7l87vfGt6EzuVels81ppEeT kW+mLgMVwPa6TYO/elNOKH4DsSG5hDIWLfzbS5508g== X-Google-Smtp-Source: ABdhPJyR3TK3AZ6vFSIVdWlbdx57iSv9BfywlkDpHw7WENtz/yeCErgNkkD7SzI8rPZAtra5UA7HzAA1/Ep30orloL4= X-Received: by 2002:a5d:618f:0:b0:20c:ffa0:95a8 with SMTP id j15-20020a5d618f000000b0020cffa095a8mr15420395wru.306.1652862148610; Wed, 18 May 2022 01:22:28 -0700 (PDT) MIME-Version: 1.0 References: <20220511214132.2281431-1-heiko@sntech.de> <20220511214132.2281431-2-heiko@sntech.de> <20220518002529.GA1928329-robh@kernel.org> In-Reply-To: <20220518002529.GA1928329-robh@kernel.org> From: Philipp Tomsich Date: Wed, 18 May 2022 10:22:17 +0200 Message-ID: Subject: Re: [PATCH v2 1/3] dt-bindings: riscv: document cbom-block-size To: Rob Herring Cc: Heiko Stuebner , palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, wefu@redhat.com, guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org, mick@ics.forth.gr, samuel@sholland.org, cmuellner@linux.com, krzk+dt@kernel.org, devicetree@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org +David Kruckemyer (who is chairing the CMO task-group within RVI). On Wed, 18 May 2022 at 02:25, Rob Herring wrote: > > On Wed, May 11, 2022 at 11:41:30PM +0200, Heiko Stuebner wrote: > > The Zicbom operates on a block-size defined for the cpu-core, > > which does not necessarily match other cache-sizes used. > > > > So add the necessary property for the system to know the core's > > block-size. > > > > Signed-off-by: Heiko Stuebner > > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index d632ac76532e..b179bfd155a3 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -63,6 +63,13 @@ properties: > > - riscv,sv48 > > - riscv,none > > > > + riscv,cbom-block-size: > > + $ref: /schemas/types.yaml#/definitions/uint32 > > Any value 0-2^32 is valid? > > > + description: > > + Blocksize in bytes for the Zicbom cache operations. The block > > + size is a property of the core itself and does not necessarily > > + match other software defined cache sizes. > > What about hardware defined cache sizes? I'm scratching my head as to > what a 'software defined cache size' is. This seems to be a misnomer, as the specification doesn't use the term and rather talks about the "size of a cache block for [operation name]". There are currently two such 'operation sizes' discoverable by software: - size of the cache block for management and prefetch instructions - size of the cache block for zero instructions For whatever it's worth, cache operations in RISC-V attempt to disassociate the underlying hardware cache geometry from software. See https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf for the CMO specification, and the discoverable parameters are listed in section 2.7. Philipp. > > + > > riscv,isa: > > description: > > Identifies the specific RISC-V instruction set architecture > > -- > > 2.35.1 > > > >