From mboxrd@z Thu Jan 1 00:00:00 1970 From: Michal Bachraty Subject: Re: [PATCH v3] clk: add si5351 i2c common clock driver Date: Tue, 9 Apr 2013 10:34:29 +0200 Message-ID: References: <6e120226-8a3c-415f-90f2-c44e7b6bbf96@googlegroups.com> <5149E85E.90701@gmail.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============3020334606861672192==" Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org Sender: "devicetree-discuss" To: Sebastian Hesselbarth Cc: Jean-Francois Moine , Mike Turquette , linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring , Russell King - ARM Linux , Dom Cobley , Stephen Warren , Andrew Morton , Rabeeh Khoury , fa.linux.kernel-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: devicetree@vger.kernel.org --===============3020334606861672192== Content-Type: multipart/alternative; boundary=047d7b10c8affedd8904d9e96bbc --047d7b10c8affedd8904d9e96bbc Content-Type: text/plain; charset=ISO-8859-1 Hi Sebastian, I posted patch for gap-less tuning. It is based on v5 of your driver. This patch was tested for tuning with 1ppm clock step. Best, Michal. On Mon, Mar 25, 2013 at 12:54 PM, Sebastian Hesselbarth < sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: > On Wed, Mar 20, 2013 at 5:48 PM, Daniel Mack wrote: > > On 20.03.2013 14:55, michal.bachraty-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote: > >> Thanks for writing this driver! I have tested your si5351 clock > >> driver and his tuning capabilities. It works well, it generates > >> proper clock frequency, but when new frequency is generated, little > >> clock gap (1ms) is generated. Si5351 datasheet and WP claims, clock > >> tuning can be without gaps - > >> > http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5350-51-Frequency-Shifting-WP.pdf > >> > >> I made some tests with Si5351A chip and I found that when tuning touch > >> only Multisynth registers, it can tune without gaps. There is no need > >> for soft PLL reset. I found also, accessing Multisynth registers is not > >> atomic, so there can be another frequency at output, while not all > >> registers are written. Writing only to one register seems to be atomic. > > Michael, > > if you don't configure the clock output to modify the pll, changing output > frequency will not alter pll config and there will be no reset of pll. > > > Yeah, but limiting possible changes to the PLLs to one single register > > also means that you cannot offer to generate all the frequencies any > > more. What could probably be done is refine the algorithm so that it > > stays 'as close as possible' to the former values, but I'm not sure how > > much work that implies. > > > > Can you provide a patch against Sebastian's v3 to do that? Then it can > > be cleanly applied on top of the driver later. > > Ack. Feel free to post a patch on top of v4 now. > > Sebastian > --047d7b10c8affedd8904d9e96bbc Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable
Hi Sebastian,

I posted patch for ga= p-less tuning. It is based on v5 of your driver.=A0 This patch was tested f= or tuning with 1ppm clock step.

Best,
Michal.


On Mon,= Mar 25, 2013 at 12:54 PM, Sebastian Hesselbarth <sebastian.= hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
On Wed, Mar 20, 2013 at 5:= 48 PM, Daniel Mack <zonque-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org= > wrote:
> On 20.03.2013 14:55, mich= al.bachraty-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote:
>> Thanks for writing this driver! I have tested your si5351 clock >> driver and his tuning capabilities. It works well, it generates >> proper clock frequency, but when new frequency is generated, littl= e
>> clock gap (1ms) is generated. Si5351 datasheet and WP claims, cloc= k
>> tuning can be without gaps -
>> http://www.silabs.c= om/Support%20Documents/TechnicalDocs/Si5350-51-Frequency-Shifting-WP.pdf
>>
>> I made some tests with Si5351A chip and I found that when tuning t= ouch
>> only Multisynth registers, it can tune without gaps. There is no n= eed
>> for soft PLL reset. I found also, accessing Multisynth registers i= s not
>> atomic, so there can be another frequency at output, while not all=
>> registers are written. Writing only to one register seems to be at= omic.

Michael,

if you don't configure the clock output to modify the pll, changing out= put
frequency will not alter pll config and there will be no reset of pll.

> Yeah, but limiting possible changes to the PLLs to one single register=
> also means that you cannot offer to generate all the frequencies any > more. What could probably be done is refine the algorithm so that it > stays 'as close as possible' to the former values, but I'm= not sure how
> much work that implies.
>
> Can you provide a patch against Sebastian's v3 to do that? Then it= can
> be cleanly applied on top of the driver later.

Ack. Feel free to post a patch on top of v4 now.

Sebastian

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