* [PATCH 0/4] Add clk and dt support for PDMA and SPI on Exynos7
@ 2014-12-19 13:23 Padmavathi Venna
2014-12-19 13:23 ` [PATCH 1/4] clk: samsung: exynos7: add gate clock for DMA block Padmavathi Venna
` (3 more replies)
0 siblings, 4 replies; 13+ messages in thread
From: Padmavathi Venna @ 2014-12-19 13:23 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc, devicetree
Cc: kgene.kim, mturquette, tomasz.figa, s.nawrocki
Add PDMA0,PDMA1 gate clock and required clks for 5 SPI channels.
Also enable the support for PDMA and 5 SPI channels in DT.
This patchset is dependent on usb clk support from Vivek in below link.
http://www.spinics.net/lists/linux-samsung-soc/msg39342.html
Padmavathi Venna (4):
clk: samsung: exynos7: add gate clock for DMA block
clk: samsung: exynos7: add clocks for SPI block
clk: samsung: exynos7: add clocks for audio block
arm64: dts: Add PDMA and SPI device tree node for exynos7
.../devicetree/bindings/clock/exynos7-clock.txt | 6 +
arch/arm64/boot/dts/exynos/exynos7.dtsi | 113 ++++++++++
drivers/clk/samsung/clk-exynos7.c | 221 +++++++++++++++++++-
include/dt-bindings/clock/exynos7-clk.h | 46 ++++-
4 files changed, 380 insertions(+), 6 deletions(-)
--
1.7.4.4
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/4] clk: samsung: exynos7: add gate clock for DMA block
2014-12-19 13:23 [PATCH 0/4] Add clk and dt support for PDMA and SPI on Exynos7 Padmavathi Venna
@ 2014-12-19 13:23 ` Padmavathi Venna
2014-12-19 13:23 ` [PATCH 2/4] clk: samsung: exynos7: add clocks for SPI block Padmavathi Venna
` (2 subsequent siblings)
3 siblings, 0 replies; 13+ messages in thread
From: Padmavathi Venna @ 2014-12-19 13:23 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc, devicetree
Cc: kgene.kim, mturquette, tomasz.figa, s.nawrocki
Add support for PDMA0 and PDMA1 gate clks.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
drivers/clk/samsung/clk-exynos7.c | 4 ++++
include/dt-bindings/clock/exynos7-clk.h | 4 +++-
2 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 3a56875..954f9a0 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -711,6 +711,10 @@ static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
"mout_aclk_fsys0_200_user",
ENABLE_ACLK_FSYS00, 19, 0, 0),
+ GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user",
+ ENABLE_ACLK_FSYS00, 3, 0, 0),
+ GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user",
+ ENABLE_ACLK_FSYS00, 4, 0, 0),
GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",
ENABLE_ACLK_FSYS01, 29, 0, 0),
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index eef2116..a6c4d8e 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -89,7 +89,9 @@
#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6
#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7
#define OSCCLK_PHY_CLKOUT_USB30_PHY 8
-#define FSYS0_NR_CLK 9
+#define ACLK_PDMA0 9
+#define ACLK_PDMA1 10
+#define FSYS0_NR_CLK 11
/* FSYS1 */
#define ACLK_MMC1 1
--
1.7.4.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/4] clk: samsung: exynos7: add clocks for SPI block
2014-12-19 13:23 [PATCH 0/4] Add clk and dt support for PDMA and SPI on Exynos7 Padmavathi Venna
2014-12-19 13:23 ` [PATCH 1/4] clk: samsung: exynos7: add gate clock for DMA block Padmavathi Venna
@ 2014-12-19 13:23 ` Padmavathi Venna
2015-01-09 11:48 ` Vivek Gautam
2014-12-19 13:23 ` [PATCH 3/4] clk: samsung: exynos7: add clocks for audio block Padmavathi Venna
2014-12-19 13:23 ` [PATCH 4/4] arm64: dts: Add PDMA and SPI device tree node for exynos7 Padmavathi Venna
3 siblings, 1 reply; 13+ messages in thread
From: Padmavathi Venna @ 2014-12-19 13:23 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc, devicetree
Cc: kgene.kim, mturquette, tomasz.figa, s.nawrocki
Add clock support for 5 SPI channels.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
drivers/clk/samsung/clk-exynos7.c | 73 +++++++++++++++++++++++++++++++
include/dt-bindings/clock/exynos7-clk.h | 22 ++++++++-
2 files changed, 93 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 954f9a0..cf5e50e 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -166,9 +166,15 @@ CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
#define MUX_SEL_TOP00 0x0200
#define MUX_SEL_TOP01 0x0204
#define MUX_SEL_TOP03 0x020C
+#define MUX_SEL_TOP0_PERIC1 0x0234
+#define MUX_SEL_TOP0_PERIC2 0x0238
#define MUX_SEL_TOP0_PERIC3 0x023C
#define DIV_TOP03 0x060C
+#define DIV_TOP0_PERIC1 0x0634
+#define DIV_TOP0_PERIC2 0x0638
#define DIV_TOP0_PERIC3 0x063C
+#define ENABLE_SCLK_TOP0_PERIC1 0x0A34
+#define ENABLE_SCLK_TOP0_PERIC2 0x0A38
#define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
/* List of parent clocks for Muxes in CMU_TOP0 */
@@ -194,9 +200,15 @@ static unsigned long top0_clk_regs[] __initdata = {
MUX_SEL_TOP00,
MUX_SEL_TOP01,
MUX_SEL_TOP03,
+ MUX_SEL_TOP0_PERIC1,
+ MUX_SEL_TOP0_PERIC2,
MUX_SEL_TOP0_PERIC3,
DIV_TOP03,
+ DIV_TOP0_PERIC1,
+ DIV_TOP0_PERIC2,
DIV_TOP0_PERIC3,
+ ENABLE_SCLK_TOP0_PERIC1,
+ ENABLE_SCLK_TOP0_PERIC2,
ENABLE_SCLK_TOP0_PERIC3,
};
@@ -218,10 +230,16 @@ static struct samsung_mux_clock top0_mux_clks[] __initdata = {
MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
+ MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
+ MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
+
+ MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
+ MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
+ MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
};
static struct samsung_div_clock top0_div_clks[] __initdata = {
@@ -230,13 +248,29 @@ static struct samsung_div_clock top0_div_clks[] __initdata = {
DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
DIV_TOP03, 20, 6),
+ DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
+ DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
+
+ DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12),
+ DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12),
+
DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
+ DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
};
static struct samsung_gate_clock top0_gate_clks[] __initdata = {
+ GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1",
+ ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
+ ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3",
+ ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2",
+ ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
@@ -245,6 +279,8 @@ static struct samsung_gate_clock top0_gate_clks[] __initdata = {
ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
+ GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4",
+ ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
};
static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
@@ -520,6 +556,7 @@ static void __init exynos7_clk_peric0_init(struct device_node *np)
/* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
#define MUX_SEL_PERIC10 0x0200
#define MUX_SEL_PERIC11 0x0204
+#define MUX_SEL_PERIC12 0x0208
#define ENABLE_PCLK_PERIC1 0x0900
#define ENABLE_SCLK_PERIC10 0x0A00
@@ -531,10 +568,16 @@ PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" };
PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" };
PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" };
PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" };
+PNAME(mout_sclk_spi0_p) = { "fin_pll", "sclk_spi0" };
+PNAME(mout_sclk_spi1_p) = { "fin_pll", "sclk_spi1" };
+PNAME(mout_sclk_spi2_p) = { "fin_pll", "sclk_spi2" };
+PNAME(mout_sclk_spi3_p) = { "fin_pll", "sclk_spi3" };
+PNAME(mout_sclk_spi4_p) = { "fin_pll", "sclk_spi4" };
static unsigned long peric1_clk_regs[] __initdata = {
MUX_SEL_PERIC10,
MUX_SEL_PERIC11,
+ MUX_SEL_PERIC12,
ENABLE_PCLK_PERIC1,
ENABLE_SCLK_PERIC10,
};
@@ -543,6 +586,16 @@ static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p,
MUX_SEL_PERIC10, 0, 1),
+ MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p,
+ MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
+ MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p,
+ MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
+ MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p,
+ MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
+ MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p,
+ MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
+ MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p,
+ MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
MUX_SEL_PERIC11, 20, 1),
MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
@@ -568,6 +621,16 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
ENABLE_PCLK_PERIC1, 10, 0, 0),
GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
ENABLE_PCLK_PERIC1, 11, 0, 0),
+ GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 12, 0, 0),
+ GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 13, 0, 0),
+ GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 14, 0, 0),
+ GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 15, 0, 0),
+ GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 16, 0, 0),
GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
ENABLE_SCLK_PERIC10, 9, 0, 0),
@@ -575,6 +638,16 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
ENABLE_SCLK_PERIC10, 10, 0, 0),
GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
ENABLE_SCLK_PERIC10, 11, 0, 0),
+ GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user",
+ ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user",
+ ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user",
+ ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user",
+ ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user",
+ ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0),
};
static struct samsung_cmu_info peric1_cmu_info __initdata = {
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index a6c4d8e..3bba9ec 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -26,7 +26,13 @@
#define CLK_SCLK_UART1 4
#define CLK_SCLK_UART2 5
#define CLK_SCLK_UART3 6
-#define TOP0_NR_CLK 7
+#define CLK_SCLK_SPI0 7
+#define CLK_SCLK_SPI1 8
+#define CLK_SCLK_SPI2 9
+#define CLK_SCLK_SPI3 10
+#define CLK_SCLK_SPI4 11
+#define CLK_SCLK_SPI5 12
+#define TOP0_NR_CLK 13
/* TOP1 */
#define DOUT_ACLK_FSYS1_200 1
@@ -70,7 +76,19 @@
#define PCLK_HSI2C6 9
#define PCLK_HSI2C7 10
#define PCLK_HSI2C8 11
-#define PERIC1_NR_CLK 12
+#define PCLK_SPI0 12
+#define PCLK_SPI1 13
+#define PCLK_SPI2 14
+#define PCLK_SPI3 15
+#define PCLK_SPI4 16
+#define PCLK_SPI5 17
+#define SCLK_SPI0 18
+#define SCLK_SPI1 19
+#define SCLK_SPI2 20
+#define SCLK_SPI3 21
+#define SCLK_SPI4 22
+#define SCLK_SPI5 23
+#define PERIC1_NR_CLK 24
/* PERIS */
#define PCLK_CHIPID 1
--
1.7.4.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/4] clk: samsung: exynos7: add clocks for audio block
2014-12-19 13:23 [PATCH 0/4] Add clk and dt support for PDMA and SPI on Exynos7 Padmavathi Venna
2014-12-19 13:23 ` [PATCH 1/4] clk: samsung: exynos7: add gate clock for DMA block Padmavathi Venna
2014-12-19 13:23 ` [PATCH 2/4] clk: samsung: exynos7: add clocks for SPI block Padmavathi Venna
@ 2014-12-19 13:23 ` Padmavathi Venna
2014-12-22 15:08 ` Sylwester Nawrocki
2015-01-13 10:29 ` Vivek Gautam
2014-12-19 13:23 ` [PATCH 4/4] arm64: dts: Add PDMA and SPI device tree node for exynos7 Padmavathi Venna
3 siblings, 2 replies; 13+ messages in thread
From: Padmavathi Venna @ 2014-12-19 13:23 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc, devicetree
Cc: kgene.kim, mturquette, tomasz.figa, s.nawrocki
Add required clk support for I2S,PCM amd SPDIF
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
.../devicetree/bindings/clock/exynos7-clock.txt | 6 +
drivers/clk/samsung/clk-exynos7.c | 144 +++++++++++++++++++-
include/dt-bindings/clock/exynos7-clk.h | 24 +++-
3 files changed, 169 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 6d3d5f8..3b439ed 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -34,6 +34,7 @@ Required Properties for Clock Controller:
- "samsung,exynos7-clock-peris"
- "samsung,exynos7-clock-fsys0"
- "samsung,exynos7-clock-fsys1"
+ - "samsung,exynos7-clock-aud"
- reg: physical base address of the controller and the length of
memory mapped region.
@@ -53,6 +54,7 @@ Input clocks for top0 clock controller:
- dout_sclk_bus1_pll
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
+ - dout_sclk_aud_pll
Input clocks for top1 clock controller:
- fin_pll
@@ -91,3 +93,7 @@ Input clocks for fsys1 clock controller:
- dout_aclk_fsys1_200
- dout_sclk_mmc0
- dout_sclk_mmc1
+
+Input clocks for aud clock controller:
+ - fin_pll
+ - fout_aud_pll
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index cf5e50e..e4bc241 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -45,6 +45,7 @@ static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
};
/* List of parent clocks for Muxes in CMU_TOPC */
+PNAME(mout_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" };
PNAME(mout_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" };
PNAME(mout_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" };
PNAME(mout_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" };
@@ -104,6 +105,7 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata = {
MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
MUX_SEL_TOPC1, 16, 1),
+ MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
@@ -125,6 +127,13 @@ static struct samsung_div_clock topc_div_clks[] __initdata = {
DIV_TOPC3, 12, 3),
DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl",
DIV_TOPC3, 16, 3),
+ DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_aud_pll_ctrl",
+ DIV_TOPC3, 28, 3),
+};
+
+static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
+ PLL_36XX_RATE(491520000, 20, 1, 0, 31457),
+ {},
};
static struct samsung_pll_clock topc_pll_clks[] __initdata = {
@@ -136,8 +145,8 @@ static struct samsung_pll_clock topc_pll_clks[] __initdata = {
BUS1_DPLL_CON0, NULL),
PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
MFC_PLL_CON0, NULL),
- PLL(pll_1460x, 0, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
- AUD_PLL_CON0, NULL),
+ PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
+ AUD_PLL_CON0, pll1460x_24mhz_tbl),
};
static struct samsung_cmu_info topc_cmu_info __initdata = {
@@ -166,13 +175,16 @@ CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
#define MUX_SEL_TOP00 0x0200
#define MUX_SEL_TOP01 0x0204
#define MUX_SEL_TOP03 0x020C
+#define MUX_SEL_TOP0_PERIC0 0x0230
#define MUX_SEL_TOP0_PERIC1 0x0234
#define MUX_SEL_TOP0_PERIC2 0x0238
#define MUX_SEL_TOP0_PERIC3 0x023C
#define DIV_TOP03 0x060C
+#define DIV_TOP0_PERIC0 0x0630
#define DIV_TOP0_PERIC1 0x0634
#define DIV_TOP0_PERIC2 0x0638
#define DIV_TOP0_PERIC3 0x063C
+#define ENABLE_SCLK_TOP0_PERIC0 0x0A30
#define ENABLE_SCLK_TOP0_PERIC1 0x0A34
#define ENABLE_SCLK_TOP0_PERIC2 0x0A38
#define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
@@ -182,6 +194,8 @@ PNAME(mout_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" };
PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" };
PNAME(mout_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll" };
PNAME(mout_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll" };
+PNAME(mout_aud_pll_p) = { "fin_pll", "dout_sclk_aud_pll" };
+
PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll",
"ffac_top0_bus0_pll_div2"};
@@ -195,24 +209,34 @@ PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll",
PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll",
"mout_top0_half_bus1_pll", "mout_top0_half_cc_pll",
"mout_top0_half_mfc_pll"};
+PNAME(mout_top0_group3) = {"ioclk_audiocdclk0",
+ "ioclk_audiocdclk1", "ioclk_spdif_extclk",
+ "mout_top0_aud_pll", "mout_top0_half_bus0_pll",
+ "mout_top0_half_bus1_pll"};
+PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll",
+ "mout_top0_half_bus0_pll", "mout_top0_half_bus1_pll"};
static unsigned long top0_clk_regs[] __initdata = {
MUX_SEL_TOP00,
MUX_SEL_TOP01,
MUX_SEL_TOP03,
+ MUX_SEL_TOP0_PERIC0,
MUX_SEL_TOP0_PERIC1,
MUX_SEL_TOP0_PERIC2,
MUX_SEL_TOP0_PERIC3,
DIV_TOP03,
+ DIV_TOP0_PERIC0,
DIV_TOP0_PERIC1,
DIV_TOP0_PERIC2,
DIV_TOP0_PERIC3,
+ ENABLE_SCLK_TOP0_PERIC0,
ENABLE_SCLK_TOP0_PERIC1,
ENABLE_SCLK_TOP0_PERIC2,
ENABLE_SCLK_TOP0_PERIC3,
};
static struct samsung_mux_clock top0_mux_clks[] __initdata = {
+ MUX(0, "mout_top0_aud_pll", mout_aud_pll_p, MUX_SEL_TOP00, 0, 1),
MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1),
MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1),
MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1),
@@ -230,6 +254,10 @@ static struct samsung_mux_clock top0_mux_clks[] __initdata = {
MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
+ MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3),
+ MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2),
+ MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2),
+
MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
@@ -248,6 +276,10 @@ static struct samsung_div_clock top0_div_clks[] __initdata = {
DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
DIV_TOP03, 20, 6),
+ DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4),
+ DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12),
+ DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10),
+
DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
@@ -262,6 +294,13 @@ static struct samsung_div_clock top0_div_clks[] __initdata = {
};
static struct samsung_gate_clock top0_gate_clks[] __initdata = {
+ GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif",
+ ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1",
+ ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1",
+ ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0),
+
GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1",
ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
@@ -631,6 +670,12 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
ENABLE_PCLK_PERIC1, 15, 0, 0),
GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user",
ENABLE_PCLK_PERIC1, 16, 0, 0),
+ GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0),
+ GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 18, 0, 0),
+ GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user",
+ ENABLE_PCLK_PERIC1, 19, 0, 0),
GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
ENABLE_SCLK_PERIC10, 9, 0, 0),
@@ -648,6 +693,12 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0),
GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user",
ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_I2S1, "sclk_i2s1_user", "dout_sclk_i2s1",
+ ENABLE_SCLK_PERIC10, 17, 0, 0),
+ GATE(SCLK_PCM1, "sclk_pcm1_user", "dout_sclk_pcm1",
+ ENABLE_SCLK_PERIC10, 18, 0, 0),
+ GATE(SCLK_SPDIF, "sclk_spdif_user", "dout_sclk_spdif",
+ ENABLE_SCLK_PERIC10, 19, 0, 0),
};
static struct samsung_cmu_info peric1_cmu_info __initdata = {
@@ -882,3 +933,92 @@ static void __init exynos7_clk_fsys1_init(struct device_node *np)
CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
exynos7_clk_fsys1_init);
+
+/* Register Offset definitions for CMU_AUD (0x114C0000) */
+#define MUX_SEL_AUD 0x0200
+#define DIV_AUD0 0x0600
+#define DIV_AUD1 0x0604
+#define ENABLE_ACLK_AUD 0x0800
+#define ENABLE_PCLK_AUD 0x0900
+#define ENABLE_SCLK_AUD 0x0A00
+
+/*
+ * List of parent clocks for Muxes in CMU_AUD
+ */
+PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" };
+PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" };
+
+static unsigned long aud_clk_regs[] __initdata = {
+ MUX_SEL_AUD,
+ DIV_AUD0,
+ DIV_AUD1,
+ ENABLE_ACLK_AUD,
+ ENABLE_PCLK_AUD,
+ ENABLE_SCLK_AUD,
+};
+
+static struct samsung_mux_clock aud_mux_clks[] __initdata = {
+ MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1),
+ MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1),
+ MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1),
+};
+
+static struct samsung_div_clock aud_div_clks[] __initdata = {
+ DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4),
+ DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4),
+ DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4),
+
+ DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4),
+ DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8),
+ DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4),
+ DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5),
+ DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4),
+};
+
+static struct samsung_gate_clock aud_gate_clks[] __initdata = {
+ GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm",
+ ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
+ GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s",
+ ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0),
+ GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0),
+ GATE(0, "sclk_slimbus", "dout_sclk_slimbus",
+ ENABLE_SCLK_AUD, 30, 0, 0),
+
+ GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0),
+ GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0),
+ GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0),
+ GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0),
+ GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0),
+ GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0),
+ GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud",
+ ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0),
+ GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud",
+ ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
+ GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0),
+ GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0),
+
+ GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0),
+ GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud",
+ ENABLE_ACLK_AUD, 28, 0, 0),
+ GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0),
+};
+
+static struct samsung_cmu_info aud_cmu_info __initdata = {
+ .mux_clks = aud_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
+ .div_clks = aud_div_clks,
+ .nr_div_clks = ARRAY_SIZE(aud_div_clks),
+ .gate_clks = aud_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
+ .nr_clk_ids = AUD_NR_CLK,
+ .clk_regs = aud_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
+};
+
+static void __init exynos7_clk_aud_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &aud_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud",
+ exynos7_clk_aud_init);
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 3bba9ec..9e5a2d8 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -17,7 +17,9 @@
#define DOUT_SCLK_CC_PLL 4
#define DOUT_SCLK_MFC_PLL 5
#define DOUT_ACLK_CCORE_133 6
-#define TOPC_NR_CLK 7
+#define DOUT_SCLK_AUD_PLL 7
+#define FOUT_AUD_PLL 8
+#define TOPC_NR_CLK 9
/* TOP0 */
#define DOUT_ACLK_PERIC1 1
@@ -32,7 +34,10 @@
#define CLK_SCLK_SPI3 10
#define CLK_SCLK_SPI4 11
#define CLK_SCLK_SPI5 12
-#define TOP0_NR_CLK 13
+#define CLK_SCLK_SPDIF 13
+#define CLK_SCLK_PCM1 14
+#define CLK_SCLK_I2S1 15
+#define TOP0_NR_CLK 16
/* TOP1 */
#define DOUT_ACLK_FSYS1_200 1
@@ -88,7 +93,13 @@
#define SCLK_SPI3 21
#define SCLK_SPI4 22
#define SCLK_SPI5 23
-#define PERIC1_NR_CLK 24
+#define PCLK_I2S1 24
+#define PCLK_PCM1 25
+#define PCLK_SPDIF 26
+#define SCLK_I2S1 27
+#define SCLK_PCM1 28
+#define SCLK_SPDIF 29
+#define PERIC1_NR_CLK 30
/* PERIS */
#define PCLK_CHIPID 1
@@ -116,4 +127,11 @@
#define ACLK_MMC0 2
#define FSYS1_NR_CLK 3
+/* AUD */
+#define SCLK_I2S 1
+#define SCLK_PCM 2
+#define PCLK_I2S 3
+#define PCLK_PCM 4
+#define ACLK_ADMA 5
+#define AUD_NR_CLK 6
#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
--
1.7.4.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 4/4] arm64: dts: Add PDMA and SPI device tree node for exynos7
2014-12-19 13:23 [PATCH 0/4] Add clk and dt support for PDMA and SPI on Exynos7 Padmavathi Venna
` (2 preceding siblings ...)
2014-12-19 13:23 ` [PATCH 3/4] clk: samsung: exynos7: add clocks for audio block Padmavathi Venna
@ 2014-12-19 13:23 ` Padmavathi Venna
3 siblings, 0 replies; 13+ messages in thread
From: Padmavathi Venna @ 2014-12-19 13:23 UTC (permalink / raw)
To: linux-arm-kernel, linux-samsung-soc, devicetree
Cc: kgene.kim, mturquette, tomasz.figa, s.nawrocki
Add PDMA0,PDMA1 and 5 SPI dt nodes for Exynos7.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
arch/arm64/boot/dts/exynos/exynos7.dtsi | 113 +++++++++++++++++++++++++++++++
1 files changed, 113 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index eeaa9b8d..db7058a 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -28,6 +28,9 @@
pinctrl7 = &pinctrl_fsys1;
pinctrl8 = &pinctrl_bus1;
pinctrl9 = &pinctrl_aud;
+ spi0 = &spi_0;
+ spi1 = &spi_1;
+ spi2 = &spi_2;
};
cpus {
@@ -573,6 +576,116 @@
samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <1>;
};
+
+ amba {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "arm,amba-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ pdma1: pdma1@10EB0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x10EB0000 0x1000>;
+ interrupts = <0 226 0>;
+ clocks = <&clock_fsys0 ACLK_PDMA1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
+
+ pdma0: pdma0@10E10000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x10E10000 0x1000>;
+ interrupts = <0 225 0>;
+ clocks = <&clock_fsys0 ACLK_PDMA0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ };
+ };
+
+ spi_0: spi@14d20000 {
+ compatible = "samsung,exynos7-spi";
+ reg = <0x14d20000 0x100>;
+ interrupts = <0 464 0>;
+ dmas = <&pdma0 7
+ &pdma0 6>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock_peric1 PCLK_SPI0>, <&clock_peric1 SCLK_SPI0>;
+ clock-names = "spi", "spi_busclk0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_bus>;
+ status = "disabled";
+ };
+
+ spi_1: spi@14d30000 {
+ compatible = "samsung,exynos7-spi";
+ reg = <0x14d30000 0x100>;
+ interrupts = <0 465 0>;
+ dmas = <&pdma0 9
+ &pdma0 8>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock_peric1 PCLK_SPI1>, <&clock_peric1 SCLK_SPI1>;
+ clock-names = "spi", "spi_busclk0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_bus>;
+ status = "disabled";
+ };
+
+ spi_2: spi@14d40000 {
+ compatible = "samsung,exynos7-spi";
+ reg = <0x14d40000 0x100>;
+ interrupts = <0 466 0>;
+ dmas = <&pdma0 11
+ &pdma0 10>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock_peric1 PCLK_SPI2>, <&clock_peric1 SCLK_SPI2>;
+ clock-names = "spi", "spi_busclk0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_bus>;
+ status = "disabled";
+ };
+
+ spi_3: spi@14d50000 {
+ compatible = "samsung,exynos7-spi";
+ reg = <0x14d50000 0x100>;
+ interrupts = <0 467 0>;
+ dmas = <&pdma0 13
+ &pdma0 12>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock_peric1 PCLK_SPI3>, <&clock_peric1 SCLK_SPI3>;
+ clock-names = "spi", "spi_busclk0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi3_bus>;
+ status = "disabled";
+ };
+
+ spi_4: spi@14d70000 {
+ compatible = "samsung,exynos7-spi";
+ reg = <0x14d70000 0x100>;
+ interrupts = <0 468 0>;
+ dmas = <&pdma0 3
+ &pdma0 2>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock_peric1 PCLK_SPI4>, <&clock_peric1 SCLK_SPI4>;
+ clock-names = "spi", "spi_busclk0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi4_bus>;
+ status = "disabled";
+ };
};
};
--
1.7.4.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 3/4] clk: samsung: exynos7: add clocks for audio block
2014-12-19 13:23 ` [PATCH 3/4] clk: samsung: exynos7: add clocks for audio block Padmavathi Venna
@ 2014-12-22 15:08 ` Sylwester Nawrocki
2015-01-13 6:16 ` Padma Venkat
2015-01-13 10:29 ` Vivek Gautam
1 sibling, 1 reply; 13+ messages in thread
From: Sylwester Nawrocki @ 2014-12-22 15:08 UTC (permalink / raw)
To: Padmavathi Venna, devicetree
Cc: linux-arm-kernel, linux-samsung-soc, kgene.kim, mturquette,
tomasz.figa
Hi,
On 19/12/14 14:23, Padmavathi Venna wrote:
> Add required clk support for I2S,PCM amd SPDIF
There is a non-trivial conflict with the MSCL CMU patch, could you
please resend rebased onto my exynos7 branch:
git://linuxtv.org/snawrocki/samsung.git for-v3.20/clk/exynos7 ?
Is exynos7420 documentation applicable to this ?
Would be nice to have someone else who has access to the SoC
documentation replied with a Reviewed-by tag.
--
Thanks,
Sylwester
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/4] clk: samsung: exynos7: add clocks for SPI block
2014-12-19 13:23 ` [PATCH 2/4] clk: samsung: exynos7: add clocks for SPI block Padmavathi Venna
@ 2015-01-09 11:48 ` Vivek Gautam
[not found] ` <CAFp+6iFzawDY1wFA-2AQUHFCk54WsaCJAOkrqvX9t7b-XugY8g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 13+ messages in thread
From: Vivek Gautam @ 2015-01-09 11:48 UTC (permalink / raw)
To: Padmavathi Venna
Cc: linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org,
Kukjin Kim, mturquette, Tomasz Figa, Sylwester Nawrocki
Hi Padma,
On Fri, Dec 19, 2014 at 6:53 PM, Padmavathi Venna <padma.v@samsung.com> wrote:
> Add clock support for 5 SPI channels.
>
> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
> ---
> drivers/clk/samsung/clk-exynos7.c | 73 +++++++++++++++++++++++++++++++
> include/dt-bindings/clock/exynos7-clk.h | 22 ++++++++-
> 2 files changed, 93 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
> index 954f9a0..cf5e50e 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -166,9 +166,15 @@ CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
> #define MUX_SEL_TOP00 0x0200
> #define MUX_SEL_TOP01 0x0204
> #define MUX_SEL_TOP03 0x020C
> +#define MUX_SEL_TOP0_PERIC1 0x0234
> +#define MUX_SEL_TOP0_PERIC2 0x0238
> #define MUX_SEL_TOP0_PERIC3 0x023C
> #define DIV_TOP03 0x060C
> +#define DIV_TOP0_PERIC1 0x0634
> +#define DIV_TOP0_PERIC2 0x0638
> #define DIV_TOP0_PERIC3 0x063C
> +#define ENABLE_SCLK_TOP0_PERIC1 0x0A34
> +#define ENABLE_SCLK_TOP0_PERIC2 0x0A38
> #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
>
> /* List of parent clocks for Muxes in CMU_TOP0 */
> @@ -194,9 +200,15 @@ static unsigned long top0_clk_regs[] __initdata = {
> MUX_SEL_TOP00,
> MUX_SEL_TOP01,
> MUX_SEL_TOP03,
> + MUX_SEL_TOP0_PERIC1,
> + MUX_SEL_TOP0_PERIC2,
> MUX_SEL_TOP0_PERIC3,
> DIV_TOP03,
> + DIV_TOP0_PERIC1,
> + DIV_TOP0_PERIC2,
> DIV_TOP0_PERIC3,
> + ENABLE_SCLK_TOP0_PERIC1,
> + ENABLE_SCLK_TOP0_PERIC2,
> ENABLE_SCLK_TOP0_PERIC3,
> };
>
> @@ -218,10 +230,16 @@ static struct samsung_mux_clock top0_mux_clks[] __initdata = {
> MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
> MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
>
> + MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
> + MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
> +
> + MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
> + MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
> MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
> MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
> MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
> MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
> + MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
> };
>
> static struct samsung_div_clock top0_div_clks[] __initdata = {
> @@ -230,13 +248,29 @@ static struct samsung_div_clock top0_div_clks[] __initdata = {
> DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
> DIV_TOP03, 20, 6),
>
> + DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
> + DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
> +
> + DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12),
> + DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12),
> +
> DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
> DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
> DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
> DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
> + DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
> };
>
> static struct samsung_gate_clock top0_gate_clks[] __initdata = {
> + GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1",
> + ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
> + ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
> +
> + GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3",
> + ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2",
> + ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
> ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
> GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
> @@ -245,6 +279,8 @@ static struct samsung_gate_clock top0_gate_clks[] __initdata = {
> ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
> GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
> ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
> + GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4",
> + ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
> };
>
> static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
> @@ -520,6 +556,7 @@ static void __init exynos7_clk_peric0_init(struct device_node *np)
> /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
> #define MUX_SEL_PERIC10 0x0200
> #define MUX_SEL_PERIC11 0x0204
> +#define MUX_SEL_PERIC12 0x0208
> #define ENABLE_PCLK_PERIC1 0x0900
> #define ENABLE_SCLK_PERIC10 0x0A00
>
> @@ -531,10 +568,16 @@ PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" };
> PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" };
> PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" };
> PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" };
> +PNAME(mout_sclk_spi0_p) = { "fin_pll", "sclk_spi0" };
> +PNAME(mout_sclk_spi1_p) = { "fin_pll", "sclk_spi1" };
> +PNAME(mout_sclk_spi2_p) = { "fin_pll", "sclk_spi2" };
> +PNAME(mout_sclk_spi3_p) = { "fin_pll", "sclk_spi3" };
> +PNAME(mout_sclk_spi4_p) = { "fin_pll", "sclk_spi4" };
>
> static unsigned long peric1_clk_regs[] __initdata = {
> MUX_SEL_PERIC10,
> MUX_SEL_PERIC11,
> + MUX_SEL_PERIC12,
> ENABLE_PCLK_PERIC1,
> ENABLE_SCLK_PERIC10,
> };
> @@ -543,6 +586,16 @@ static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
> MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p,
> MUX_SEL_PERIC10, 0, 1),
>
> + MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p,
> + MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
> + MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p,
> + MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
> + MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p,
> + MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
> + MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p,
> + MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
> + MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p,
> + MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
> MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
> MUX_SEL_PERIC11, 20, 1),
> MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
> @@ -568,6 +621,16 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
> ENABLE_PCLK_PERIC1, 10, 0, 0),
> GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
> ENABLE_PCLK_PERIC1, 11, 0, 0),
> + GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user",
> + ENABLE_PCLK_PERIC1, 12, 0, 0),
> + GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user",
> + ENABLE_PCLK_PERIC1, 13, 0, 0),
> + GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user",
> + ENABLE_PCLK_PERIC1, 14, 0, 0),
> + GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user",
> + ENABLE_PCLK_PERIC1, 15, 0, 0),
> + GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user",
> + ENABLE_PCLK_PERIC1, 16, 0, 0),
>
> GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
> ENABLE_SCLK_PERIC10, 9, 0, 0),
> @@ -575,6 +638,16 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
> ENABLE_SCLK_PERIC10, 10, 0, 0),
> GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
> ENABLE_SCLK_PERIC10, 11, 0, 0),
> + GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user",
> + ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0),
> + GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user",
> + ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0),
> + GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user",
> + ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0),
> + GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user",
> + ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0),
> + GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user",
> + ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0),
> };
>
> static struct samsung_cmu_info peric1_cmu_info __initdata = {
> diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
> index a6c4d8e..3bba9ec 100644
> --- a/include/dt-bindings/clock/exynos7-clk.h
> +++ b/include/dt-bindings/clock/exynos7-clk.h
> @@ -26,7 +26,13 @@
> #define CLK_SCLK_UART1 4
> #define CLK_SCLK_UART2 5
> #define CLK_SCLK_UART3 6
> -#define TOP0_NR_CLK 7
> +#define CLK_SCLK_SPI0 7
> +#define CLK_SCLK_SPI1 8
> +#define CLK_SCLK_SPI2 9
> +#define CLK_SCLK_SPI3 10
> +#define CLK_SCLK_SPI4 11
> +#define CLK_SCLK_SPI5 12
I don't see this CLK_SCLK_SPI5 being used anywhere in the patch.
Possibly you didn't want to add it here.
> +#define TOP0_NR_CLK 13
>
> /* TOP1 */
> #define DOUT_ACLK_FSYS1_200 1
> @@ -70,7 +76,19 @@
> #define PCLK_HSI2C6 9
> #define PCLK_HSI2C7 10
> #define PCLK_HSI2C8 11
> -#define PERIC1_NR_CLK 12
> +#define PCLK_SPI0 12
> +#define PCLK_SPI1 13
> +#define PCLK_SPI2 14
> +#define PCLK_SPI3 15
> +#define PCLK_SPI4 16
> +#define PCLK_SPI5 17
> +#define SCLK_SPI0 18
> +#define SCLK_SPI1 19
> +#define SCLK_SPI2 20
> +#define SCLK_SPI3 21
> +#define SCLK_SPI4 22
> +#define SCLK_SPI5 23
Same here for SCLK_SPI5, unused in the patch.
[snip]
The rest all looks good in this patch. I have also verified from the Exynos7 UM.
--
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/4] clk: samsung: exynos7: add clocks for SPI block
[not found] ` <CAFp+6iFzawDY1wFA-2AQUHFCk54WsaCJAOkrqvX9t7b-XugY8g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2015-01-09 11:54 ` Vivek Gautam
2015-01-13 6:10 ` Padma Venkat
0 siblings, 1 reply; 13+ messages in thread
From: Vivek Gautam @ 2015-01-09 11:54 UTC (permalink / raw)
To: Padmavathi Venna
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Kukjin Kim,
mturquette-QSEj5FYQhm4dnm+yROfE0A, Tomasz Figa,
Sylwester Nawrocki
On Fri, Jan 9, 2015 at 5:18 PM, Vivek Gautam <gautamvivek1987-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> Hi Padma,
>
>
> On Fri, Dec 19, 2014 at 6:53 PM, Padmavathi Venna <padma.v-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote:
>> Add clock support for 5 SPI channels.
>>
>> Signed-off-by: Padmavathi Venna <padma.v-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>> ---
>> drivers/clk/samsung/clk-exynos7.c | 73 +++++++++++++++++++++++++++++++
>> include/dt-bindings/clock/exynos7-clk.h | 22 ++++++++-
>> 2 files changed, 93 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
>> index 954f9a0..cf5e50e 100644
>> --- a/drivers/clk/samsung/clk-exynos7.c
>> +++ b/drivers/clk/samsung/clk-exynos7.c
>> @@ -166,9 +166,15 @@ CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
>> #define MUX_SEL_TOP00 0x0200
>> #define MUX_SEL_TOP01 0x0204
>> #define MUX_SEL_TOP03 0x020C
>> +#define MUX_SEL_TOP0_PERIC1 0x0234
>> +#define MUX_SEL_TOP0_PERIC2 0x0238
>> #define MUX_SEL_TOP0_PERIC3 0x023C
>> #define DIV_TOP03 0x060C
>> +#define DIV_TOP0_PERIC1 0x0634
>> +#define DIV_TOP0_PERIC2 0x0638
>> #define DIV_TOP0_PERIC3 0x063C
>> +#define ENABLE_SCLK_TOP0_PERIC1 0x0A34
>> +#define ENABLE_SCLK_TOP0_PERIC2 0x0A38
>> #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
>>
>> /* List of parent clocks for Muxes in CMU_TOP0 */
>> @@ -194,9 +200,15 @@ static unsigned long top0_clk_regs[] __initdata = {
>> MUX_SEL_TOP00,
>> MUX_SEL_TOP01,
>> MUX_SEL_TOP03,
>> + MUX_SEL_TOP0_PERIC1,
>> + MUX_SEL_TOP0_PERIC2,
>> MUX_SEL_TOP0_PERIC3,
>> DIV_TOP03,
>> + DIV_TOP0_PERIC1,
>> + DIV_TOP0_PERIC2,
>> DIV_TOP0_PERIC3,
>> + ENABLE_SCLK_TOP0_PERIC1,
>> + ENABLE_SCLK_TOP0_PERIC2,
>> ENABLE_SCLK_TOP0_PERIC3,
>> };
>>
>> @@ -218,10 +230,16 @@ static struct samsung_mux_clock top0_mux_clks[] __initdata = {
>> MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
>> MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
>>
>> + MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
>> + MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
>> +
>> + MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
>> + MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
>> MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
>> MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
>> MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
>> MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
>> + MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
>> };
>>
>> static struct samsung_div_clock top0_div_clks[] __initdata = {
>> @@ -230,13 +248,29 @@ static struct samsung_div_clock top0_div_clks[] __initdata = {
>> DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
>> DIV_TOP03, 20, 6),
>>
>> + DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
>> + DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
>> +
>> + DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12),
>> + DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12),
>> +
>> DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
>> DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
>> DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
>> DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
>> + DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
>> };
>>
>> static struct samsung_gate_clock top0_gate_clks[] __initdata = {
>> + GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1",
>> + ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
>> + GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
>> + ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
>> +
>> + GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3",
>> + ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
>> + GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2",
>> + ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
>> GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
>> ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
>> GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
>> @@ -245,6 +279,8 @@ static struct samsung_gate_clock top0_gate_clks[] __initdata = {
>> ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
>> GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
>> ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
>> + GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4",
>> + ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
>> };
>>
>> static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
>> @@ -520,6 +556,7 @@ static void __init exynos7_clk_peric0_init(struct device_node *np)
>> /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
>> #define MUX_SEL_PERIC10 0x0200
>> #define MUX_SEL_PERIC11 0x0204
>> +#define MUX_SEL_PERIC12 0x0208
>> #define ENABLE_PCLK_PERIC1 0x0900
>> #define ENABLE_SCLK_PERIC10 0x0A00
>>
>> @@ -531,10 +568,16 @@ PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" };
>> PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" };
>> PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" };
>> PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" };
>> +PNAME(mout_sclk_spi0_p) = { "fin_pll", "sclk_spi0" };
>> +PNAME(mout_sclk_spi1_p) = { "fin_pll", "sclk_spi1" };
>> +PNAME(mout_sclk_spi2_p) = { "fin_pll", "sclk_spi2" };
>> +PNAME(mout_sclk_spi3_p) = { "fin_pll", "sclk_spi3" };
>> +PNAME(mout_sclk_spi4_p) = { "fin_pll", "sclk_spi4" };
>>
>> static unsigned long peric1_clk_regs[] __initdata = {
>> MUX_SEL_PERIC10,
>> MUX_SEL_PERIC11,
>> + MUX_SEL_PERIC12,
>> ENABLE_PCLK_PERIC1,
>> ENABLE_SCLK_PERIC10,
>> };
>> @@ -543,6 +586,16 @@ static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
>> MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p,
>> MUX_SEL_PERIC10, 0, 1),
>>
>> + MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p,
>> + MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
>> + MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p,
>> + MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
>> + MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p,
>> + MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
>> + MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p,
>> + MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
>> + MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p,
>> + MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
>> MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
>> MUX_SEL_PERIC11, 20, 1),
>> MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
>> @@ -568,6 +621,16 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
>> ENABLE_PCLK_PERIC1, 10, 0, 0),
>> GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
>> ENABLE_PCLK_PERIC1, 11, 0, 0),
>> + GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user",
>> + ENABLE_PCLK_PERIC1, 12, 0, 0),
>> + GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user",
>> + ENABLE_PCLK_PERIC1, 13, 0, 0),
>> + GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user",
>> + ENABLE_PCLK_PERIC1, 14, 0, 0),
>> + GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user",
>> + ENABLE_PCLK_PERIC1, 15, 0, 0),
>> + GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user",
>> + ENABLE_PCLK_PERIC1, 16, 0, 0),
>>
>> GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
>> ENABLE_SCLK_PERIC10, 9, 0, 0),
>> @@ -575,6 +638,16 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
>> ENABLE_SCLK_PERIC10, 10, 0, 0),
>> GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
>> ENABLE_SCLK_PERIC10, 11, 0, 0),
>> + GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user",
>> + ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0),
>> + GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user",
>> + ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0),
>> + GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user",
>> + ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0),
>> + GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user",
>> + ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0),
>> + GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user",
>> + ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0),
>> };
>>
>> static struct samsung_cmu_info peric1_cmu_info __initdata = {
>> diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
>> index a6c4d8e..3bba9ec 100644
>> --- a/include/dt-bindings/clock/exynos7-clk.h
>> +++ b/include/dt-bindings/clock/exynos7-clk.h
>> @@ -26,7 +26,13 @@
>> #define CLK_SCLK_UART1 4
>> #define CLK_SCLK_UART2 5
>> #define CLK_SCLK_UART3 6
>> -#define TOP0_NR_CLK 7
>> +#define CLK_SCLK_SPI0 7
>> +#define CLK_SCLK_SPI1 8
>> +#define CLK_SCLK_SPI2 9
>> +#define CLK_SCLK_SPI3 10
>> +#define CLK_SCLK_SPI4 11
>> +#define CLK_SCLK_SPI5 12
>
> I don't see this CLK_SCLK_SPI5 being used anywhere in the patch.
> Possibly you didn't want to add it here.
>
>> +#define TOP0_NR_CLK 13
>>
>> /* TOP1 */
>> #define DOUT_ACLK_FSYS1_200 1
>> @@ -70,7 +76,19 @@
>> #define PCLK_HSI2C6 9
>> #define PCLK_HSI2C7 10
>> #define PCLK_HSI2C8 11
>> -#define PERIC1_NR_CLK 12
>> +#define PCLK_SPI0 12
>> +#define PCLK_SPI1 13
>> +#define PCLK_SPI2 14
>> +#define PCLK_SPI3 15
>> +#define PCLK_SPI4 16
>> +#define PCLK_SPI5 17
>> +#define SCLK_SPI0 18
>> +#define SCLK_SPI1 19
>> +#define SCLK_SPI2 20
>> +#define SCLK_SPI3 21
>> +#define SCLK_SPI4 22
>> +#define SCLK_SPI5 23
>
> Same here for SCLK_SPI5, unused in the patch.
>
> [snip]
>
> The rest all looks good in this patch. I have also verified from the Exynos7 UM.
missed it earlier. You may also want to add update documentation for
clock sources
of peric1 block.
--
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/4] clk: samsung: exynos7: add clocks for SPI block
2015-01-09 11:54 ` Vivek Gautam
@ 2015-01-13 6:10 ` Padma Venkat
0 siblings, 0 replies; 13+ messages in thread
From: Padma Venkat @ 2015-01-13 6:10 UTC (permalink / raw)
To: Vivek Gautam
Cc: Padmavathi Venna, linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org,
Kukjin Kim, mturquette, Tomasz Figa, Sylwester Nawrocki
Hi ViVek,
On 1/9/15, Vivek Gautam <gautamvivek1987@gmail.com> wrote:
> On Fri, Jan 9, 2015 at 5:18 PM, Vivek Gautam <gautamvivek1987@gmail.com>
> wrote:
>> Hi Padma,
>>
>>
>> On Fri, Dec 19, 2014 at 6:53 PM, Padmavathi Venna <padma.v@samsung.com>
>> wrote:
>>> Add clock support for 5 SPI channels.
>>>
>>> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
>>> ---
[snip]
>> Same here for SCLK_SPI5, unused in the patch.
ok.
>>
>> [snip]
>>
>> The rest all looks good in this patch. I have also verified from the
>> Exynos7 UM.
>
> missed it earlier. You may also want to add update documentation for
> clock sources
> of peric1 block.
I will add the required source clks.
Thanks for the review.
Padma
>
>
> --
> Best Regards
> Vivek Gautam
> Samsung R&D Institute, Bangalore
> India
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/4] clk: samsung: exynos7: add clocks for audio block
2014-12-22 15:08 ` Sylwester Nawrocki
@ 2015-01-13 6:16 ` Padma Venkat
0 siblings, 0 replies; 13+ messages in thread
From: Padma Venkat @ 2015-01-13 6:16 UTC (permalink / raw)
To: Sylwester Nawrocki
Cc: Padmavathi Venna, devicetree, linux-arm-kernel, linux-samsung-soc,
kgene.kim, mturquette, tomasz.figa
Hi Sylwester,
On 12/22/14, Sylwester Nawrocki <s.nawrocki@samsung.com> wrote:
> Hi,
>
> On 19/12/14 14:23, Padmavathi Venna wrote:
>> Add required clk support for I2S,PCM amd SPDIF
>
> There is a non-trivial conflict with the MSCL CMU patch, could you
> please resend rebased onto my exynos7 branch:
Ok. I willl rebase the patch on your tree.
>
> git://linuxtv.org/snawrocki/samsung.git for-v3.20/clk/exynos7 ?
>
> Is exynos7420 documentation applicable to this ?
This is applicable only for exynos7.
> Would be nice to have someone else who has access to the SoC
> documentation replied with a Reviewed-by tag.
>
> --
> Thanks,
> Sylwester
Thanks
Padma
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
> in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/4] clk: samsung: exynos7: add clocks for audio block
2014-12-19 13:23 ` [PATCH 3/4] clk: samsung: exynos7: add clocks for audio block Padmavathi Venna
2014-12-22 15:08 ` Sylwester Nawrocki
@ 2015-01-13 10:29 ` Vivek Gautam
2015-01-15 5:49 ` Padma Venkat
1 sibling, 1 reply; 13+ messages in thread
From: Vivek Gautam @ 2015-01-13 10:29 UTC (permalink / raw)
To: Padmavathi Venna
Cc: linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org,
Kukjin Kim, Mike Turquette, Tomasz Figa, Sylwester Nawrocki
Hi Padma,
On Fri, Dec 19, 2014 at 6:53 PM, Padmavathi Venna <padma.v@samsung.com> wrote:
> Add required clk support for I2S,PCM amd SPDIF
>
> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
> ---
verified from Exynos7 datasheet. The patch looks good.
Reviewed-by: Vivek Gautam <gautam.vivek@samsung.com>
> .../devicetree/bindings/clock/exynos7-clock.txt | 6 +
> drivers/clk/samsung/clk-exynos7.c | 144 +++++++++++++++++++-
> include/dt-bindings/clock/exynos7-clk.h | 24 +++-
> 3 files changed, 169 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
> index 6d3d5f8..3b439ed 100644
> --- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
> @@ -34,6 +34,7 @@ Required Properties for Clock Controller:
> - "samsung,exynos7-clock-peris"
> - "samsung,exynos7-clock-fsys0"
> - "samsung,exynos7-clock-fsys1"
> + - "samsung,exynos7-clock-aud"
>
> - reg: physical base address of the controller and the length of
> memory mapped region.
> @@ -53,6 +54,7 @@ Input clocks for top0 clock controller:
> - dout_sclk_bus1_pll
> - dout_sclk_cc_pll
> - dout_sclk_mfc_pll
> + - dout_sclk_aud_pll
>
> Input clocks for top1 clock controller:
> - fin_pll
> @@ -91,3 +93,7 @@ Input clocks for fsys1 clock controller:
> - dout_aclk_fsys1_200
> - dout_sclk_mmc0
> - dout_sclk_mmc1
> +
> +Input clocks for aud clock controller:
> + - fin_pll
> + - fout_aud_pll
> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
> index cf5e50e..e4bc241 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -45,6 +45,7 @@ static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
> };
>
> /* List of parent clocks for Muxes in CMU_TOPC */
> +PNAME(mout_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" };
> PNAME(mout_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" };
> PNAME(mout_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" };
> PNAME(mout_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" };
> @@ -104,6 +105,7 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata = {
>
> MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
> MUX_SEL_TOPC1, 16, 1),
> + MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
>
> MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
>
> @@ -125,6 +127,13 @@ static struct samsung_div_clock topc_div_clks[] __initdata = {
> DIV_TOPC3, 12, 3),
> DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl",
> DIV_TOPC3, 16, 3),
> + DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_aud_pll_ctrl",
> + DIV_TOPC3, 28, 3),
> +};
> +
> +static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
> + PLL_36XX_RATE(491520000, 20, 1, 0, 31457),
> + {},
> };
>
> static struct samsung_pll_clock topc_pll_clks[] __initdata = {
> @@ -136,8 +145,8 @@ static struct samsung_pll_clock topc_pll_clks[] __initdata = {
> BUS1_DPLL_CON0, NULL),
> PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
> MFC_PLL_CON0, NULL),
> - PLL(pll_1460x, 0, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
> - AUD_PLL_CON0, NULL),
> + PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
> + AUD_PLL_CON0, pll1460x_24mhz_tbl),
> };
>
> static struct samsung_cmu_info topc_cmu_info __initdata = {
> @@ -166,13 +175,16 @@ CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
> #define MUX_SEL_TOP00 0x0200
> #define MUX_SEL_TOP01 0x0204
> #define MUX_SEL_TOP03 0x020C
> +#define MUX_SEL_TOP0_PERIC0 0x0230
> #define MUX_SEL_TOP0_PERIC1 0x0234
> #define MUX_SEL_TOP0_PERIC2 0x0238
> #define MUX_SEL_TOP0_PERIC3 0x023C
> #define DIV_TOP03 0x060C
> +#define DIV_TOP0_PERIC0 0x0630
> #define DIV_TOP0_PERIC1 0x0634
> #define DIV_TOP0_PERIC2 0x0638
> #define DIV_TOP0_PERIC3 0x063C
> +#define ENABLE_SCLK_TOP0_PERIC0 0x0A30
> #define ENABLE_SCLK_TOP0_PERIC1 0x0A34
> #define ENABLE_SCLK_TOP0_PERIC2 0x0A38
> #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
> @@ -182,6 +194,8 @@ PNAME(mout_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" };
> PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" };
> PNAME(mout_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll" };
> PNAME(mout_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll" };
> +PNAME(mout_aud_pll_p) = { "fin_pll", "dout_sclk_aud_pll" };
> +
nit: unnecessary additional line.
>
> PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll",
> "ffac_top0_bus0_pll_div2"};
> @@ -195,24 +209,34 @@ PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll",
> PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll",
> "mout_top0_half_bus1_pll", "mout_top0_half_cc_pll",
> "mout_top0_half_mfc_pll"};
> +PNAME(mout_top0_group3) = {"ioclk_audiocdclk0",
> + "ioclk_audiocdclk1", "ioclk_spdif_extclk",
> + "mout_top0_aud_pll", "mout_top0_half_bus0_pll",
> + "mout_top0_half_bus1_pll"};
> +PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll",
> + "mout_top0_half_bus0_pll", "mout_top0_half_bus1_pll"};
>
> static unsigned long top0_clk_regs[] __initdata = {
> MUX_SEL_TOP00,
> MUX_SEL_TOP01,
> MUX_SEL_TOP03,
> + MUX_SEL_TOP0_PERIC0,
> MUX_SEL_TOP0_PERIC1,
> MUX_SEL_TOP0_PERIC2,
> MUX_SEL_TOP0_PERIC3,
> DIV_TOP03,
> + DIV_TOP0_PERIC0,
> DIV_TOP0_PERIC1,
> DIV_TOP0_PERIC2,
> DIV_TOP0_PERIC3,
> + ENABLE_SCLK_TOP0_PERIC0,
> ENABLE_SCLK_TOP0_PERIC1,
> ENABLE_SCLK_TOP0_PERIC2,
> ENABLE_SCLK_TOP0_PERIC3,
> };
>
> static struct samsung_mux_clock top0_mux_clks[] __initdata = {
> + MUX(0, "mout_top0_aud_pll", mout_aud_pll_p, MUX_SEL_TOP00, 0, 1),
> MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1),
> MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1),
> MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1),
> @@ -230,6 +254,10 @@ static struct samsung_mux_clock top0_mux_clks[] __initdata = {
> MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
> MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
>
> + MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3),
> + MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2),
> + MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2),
> +
> MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
> MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
>
> @@ -248,6 +276,10 @@ static struct samsung_div_clock top0_div_clks[] __initdata = {
> DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
> DIV_TOP03, 20, 6),
>
> + DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4),
> + DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12),
> + DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10),
> +
> DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
> DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
>
> @@ -262,6 +294,13 @@ static struct samsung_div_clock top0_div_clks[] __initdata = {
> };
>
> static struct samsung_gate_clock top0_gate_clks[] __initdata = {
> + GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif",
> + ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1",
> + ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1",
> + ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0),
> +
> GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1",
> ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
> GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
> @@ -631,6 +670,12 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
> ENABLE_PCLK_PERIC1, 15, 0, 0),
> GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user",
> ENABLE_PCLK_PERIC1, 16, 0, 0),
> + GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user",
> + ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0),
> + GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user",
> + ENABLE_PCLK_PERIC1, 18, 0, 0),
> + GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user",
> + ENABLE_PCLK_PERIC1, 19, 0, 0),
>
> GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
> ENABLE_SCLK_PERIC10, 9, 0, 0),
> @@ -648,6 +693,12 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
> ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0),
> GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user",
> ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0),
> + GATE(SCLK_I2S1, "sclk_i2s1_user", "dout_sclk_i2s1",
> + ENABLE_SCLK_PERIC10, 17, 0, 0),
> + GATE(SCLK_PCM1, "sclk_pcm1_user", "dout_sclk_pcm1",
> + ENABLE_SCLK_PERIC10, 18, 0, 0),
> + GATE(SCLK_SPDIF, "sclk_spdif_user", "dout_sclk_spdif",
> + ENABLE_SCLK_PERIC10, 19, 0, 0),
> };
>
> static struct samsung_cmu_info peric1_cmu_info __initdata = {
> @@ -882,3 +933,92 @@ static void __init exynos7_clk_fsys1_init(struct device_node *np)
>
> CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
> exynos7_clk_fsys1_init);
> +
> +/* Register Offset definitions for CMU_AUD (0x114C0000) */
> +#define MUX_SEL_AUD 0x0200
> +#define DIV_AUD0 0x0600
> +#define DIV_AUD1 0x0604
> +#define ENABLE_ACLK_AUD 0x0800
> +#define ENABLE_PCLK_AUD 0x0900
> +#define ENABLE_SCLK_AUD 0x0A00
> +
> +/*
> + * List of parent clocks for Muxes in CMU_AUD
> + */
> +PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" };
> +PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" };
> +
> +static unsigned long aud_clk_regs[] __initdata = {
> + MUX_SEL_AUD,
> + DIV_AUD0,
> + DIV_AUD1,
> + ENABLE_ACLK_AUD,
> + ENABLE_PCLK_AUD,
> + ENABLE_SCLK_AUD,
> +};
> +
> +static struct samsung_mux_clock aud_mux_clks[] __initdata = {
> + MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1),
> + MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1),
> + MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1),
> +};
> +
> +static struct samsung_div_clock aud_div_clks[] __initdata = {
> + DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4),
> + DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4),
> + DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4),
> +
> + DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4),
> + DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8),
> + DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4),
> + DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5),
> + DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4),
> +};
> +
> +static struct samsung_gate_clock aud_gate_clks[] __initdata = {
> + GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm",
> + ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
> + GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s",
> + ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0),
> + GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0),
> + GATE(0, "sclk_slimbus", "dout_sclk_slimbus",
> + ENABLE_SCLK_AUD, 30, 0, 0),
> +
> + GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0),
> + GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0),
> + GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0),
> + GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0),
> + GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0),
> + GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0),
> + GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud",
> + ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0),
> + GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud",
> + ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
> + GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0),
> + GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0),
> +
> + GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0),
> + GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud",
> + ENABLE_ACLK_AUD, 28, 0, 0),
> + GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0),
> +};
> +
> +static struct samsung_cmu_info aud_cmu_info __initdata = {
> + .mux_clks = aud_mux_clks,
> + .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
> + .div_clks = aud_div_clks,
> + .nr_div_clks = ARRAY_SIZE(aud_div_clks),
> + .gate_clks = aud_gate_clks,
> + .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
> + .nr_clk_ids = AUD_NR_CLK,
> + .clk_regs = aud_clk_regs,
> + .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
> +};
> +
> +static void __init exynos7_clk_aud_init(struct device_node *np)
> +{
> + samsung_cmu_register_one(np, &aud_cmu_info);
> +}
> +
> +CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud",
> + exynos7_clk_aud_init);
> diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
> index 3bba9ec..9e5a2d8 100644
> --- a/include/dt-bindings/clock/exynos7-clk.h
> +++ b/include/dt-bindings/clock/exynos7-clk.h
> @@ -17,7 +17,9 @@
> #define DOUT_SCLK_CC_PLL 4
> #define DOUT_SCLK_MFC_PLL 5
> #define DOUT_ACLK_CCORE_133 6
> -#define TOPC_NR_CLK 7
> +#define DOUT_SCLK_AUD_PLL 7
> +#define FOUT_AUD_PLL 8
> +#define TOPC_NR_CLK 9
>
> /* TOP0 */
> #define DOUT_ACLK_PERIC1 1
> @@ -32,7 +34,10 @@
> #define CLK_SCLK_SPI3 10
> #define CLK_SCLK_SPI4 11
> #define CLK_SCLK_SPI5 12
> -#define TOP0_NR_CLK 13
> +#define CLK_SCLK_SPDIF 13
> +#define CLK_SCLK_PCM1 14
> +#define CLK_SCLK_I2S1 15
> +#define TOP0_NR_CLK 16
>
> /* TOP1 */
> #define DOUT_ACLK_FSYS1_200 1
> @@ -88,7 +93,13 @@
> #define SCLK_SPI3 21
> #define SCLK_SPI4 22
> #define SCLK_SPI5 23
> -#define PERIC1_NR_CLK 24
> +#define PCLK_I2S1 24
> +#define PCLK_PCM1 25
> +#define PCLK_SPDIF 26
> +#define SCLK_I2S1 27
> +#define SCLK_PCM1 28
> +#define SCLK_SPDIF 29
> +#define PERIC1_NR_CLK 30
>
> /* PERIS */
> #define PCLK_CHIPID 1
> @@ -116,4 +127,11 @@
> #define ACLK_MMC0 2
> #define FSYS1_NR_CLK 3
>
> +/* AUD */
> +#define SCLK_I2S 1
> +#define SCLK_PCM 2
> +#define PCLK_I2S 3
> +#define PCLK_PCM 4
> +#define ACLK_ADMA 5
> +#define AUD_NR_CLK 6
> #endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
> --
> 1.7.4.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/4] clk: samsung: exynos7: add clocks for audio block
2015-01-13 10:29 ` Vivek Gautam
@ 2015-01-15 5:49 ` Padma Venkat
2015-01-15 14:24 ` Sylwester Nawrocki
0 siblings, 1 reply; 13+ messages in thread
From: Padma Venkat @ 2015-01-15 5:49 UTC (permalink / raw)
To: Vivek Gautam
Cc: Padmavathi Venna, linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org,
Kukjin Kim, Mike Turquette, Tomasz Figa, Sylwester Nawrocki
Hi Vivek,
On 1/13/15, Vivek Gautam <gautamvivek1987@gmail.com> wrote:
> Hi Padma,
>
>
> On Fri, Dec 19, 2014 at 6:53 PM, Padmavathi Venna <padma.v@samsung.com>
> wrote:
>> Add required clk support for I2S,PCM amd SPDIF
>>
>> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
>> ---
>
> verified from Exynos7 datasheet. The patch looks good.
> Reviewed-by: Vivek Gautam <gautam.vivek@samsung.com>
>
Thanks for the review.
Hi Sylwester,
I posted patches after re-basing on your tree and after incorporating
all comments from Vivek.
Below is the link
http://www.spinics.net/lists/linux-samsung-soc/msg40992.html
Can you pick the patches?
Thanks
Padma
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/4] clk: samsung: exynos7: add clocks for audio block
2015-01-15 5:49 ` Padma Venkat
@ 2015-01-15 14:24 ` Sylwester Nawrocki
0 siblings, 0 replies; 13+ messages in thread
From: Sylwester Nawrocki @ 2015-01-15 14:24 UTC (permalink / raw)
To: Padma Venkat, Vivek Gautam
Cc: Padmavathi Venna, linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org,
Kukjin Kim, Mike Turquette, Tomasz Figa
Hi,
On 15/01/15 06:49, Padma Venkat wrote:
> I posted patches after re-basing on your tree and after incorporating
> all comments from Vivek.
> Below is the link
> http://www.spinics.net/lists/linux-samsung-soc/msg40992.html
>
> Can you pick the patches?
Sure, I'm not forgetting it. I've updated the exynos7 branch with your
v2 patches.
Thanks!
Sylwester
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2015-01-15 14:24 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-12-19 13:23 [PATCH 0/4] Add clk and dt support for PDMA and SPI on Exynos7 Padmavathi Venna
2014-12-19 13:23 ` [PATCH 1/4] clk: samsung: exynos7: add gate clock for DMA block Padmavathi Venna
2014-12-19 13:23 ` [PATCH 2/4] clk: samsung: exynos7: add clocks for SPI block Padmavathi Venna
2015-01-09 11:48 ` Vivek Gautam
[not found] ` <CAFp+6iFzawDY1wFA-2AQUHFCk54WsaCJAOkrqvX9t7b-XugY8g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-01-09 11:54 ` Vivek Gautam
2015-01-13 6:10 ` Padma Venkat
2014-12-19 13:23 ` [PATCH 3/4] clk: samsung: exynos7: add clocks for audio block Padmavathi Venna
2014-12-22 15:08 ` Sylwester Nawrocki
2015-01-13 6:16 ` Padma Venkat
2015-01-13 10:29 ` Vivek Gautam
2015-01-15 5:49 ` Padma Venkat
2015-01-15 14:24 ` Sylwester Nawrocki
2014-12-19 13:23 ` [PATCH 4/4] arm64: dts: Add PDMA and SPI device tree node for exynos7 Padmavathi Venna
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