From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA542C48BE5 for ; Tue, 22 Jun 2021 04:49:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B738161289 for ; Tue, 22 Jun 2021 04:49:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229574AbhFVEvm (ORCPT ); Tue, 22 Jun 2021 00:51:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229835AbhFVEvm (ORCPT ); Tue, 22 Jun 2021 00:51:42 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D607FC06175F for ; Mon, 21 Jun 2021 21:49:25 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id d11so19614444wrm.0 for ; Mon, 21 Jun 2021 21:49:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=LZDUAnqEXjRVZWh1a1xJ1KodfKynosGX+MGHfcnE+kU=; b=bH4f1th7fB3/XSYd6w/iVmgPpxVgsJ3aJmbLqWedYwp9i75zoJ/imdZCICERT9g3fF YULFqKNz6F/epgqr5mdJIh8/upyxVLtWGUfYbRCK/VCu95PPVKJPY4c6VsKfGmpqKBSt fln5qvXh9p+ilYo7R3rYscL4zn+fiFxs6ol9N82k4JbR0NeYyqMJ573O18CNCM+YGeoN xADdUH/x4BzN63KiLgP5XXLurHCsRxXwOPZEwIUXZeyVOQUewlaS2srVZxhuWXsz/28o ENV3xIu69pdHqngak3AEYJSHE07V/kUTq+c8mhLcDhI25noNGdNYh/sJLGE9WQeawOhQ WU7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=LZDUAnqEXjRVZWh1a1xJ1KodfKynosGX+MGHfcnE+kU=; b=tQaIM9YmDvOnroOtUBGWHY4eVYIKev52Cd+7NXUYStrud4P1415E7TdYe8uGMz5QJE PCsvB4P53oGuBq4QxeZeWCuFJgRe+wUSuYjAsw+vkMHDEAU7d36l+Frqb/7E+YpjcwAr T5+fXDCQyXWIEiJz4wuPVVfO0VkkMDFucDiskK9FMzpc7WkOxKgA0joiwaH1GwWYOE8Q RyBPGP9Rn/HERP8toD5Kp+u1cKOUPjOf17n+zpVL2vjvABNx3MEdELmcIymXRH7Mt5Zr Cy5eYTZNTfSmymQN8Gt5RmCoNg9bqWGBPBgQfwItUzBNt642eDfGNd6isolOAPPREN8X +zYA== X-Gm-Message-State: AOAM533300+kwA8FgC98IHAkeeYw6Hh2cRL9moyo9ODX2dBCLH6dWYUz QCLMbe3b0YkKXwYxrFbZzQ3aSNwPTiXmUoAnou1yIw== X-Google-Smtp-Source: ABdhPJwH28VdMClZV5cXRWjOAW5ajVp3FB9zxBUuvaVaxTUHQtU/5jIhNmSJ1wgDKuI5HeKx8JSfTJqVrJOC3H7w8IY= X-Received: by 2002:a5d:6e81:: with SMTP id k1mr2226740wrz.144.1624337362425; Mon, 21 Jun 2021 21:49:22 -0700 (PDT) MIME-Version: 1.0 References: <20210610052221.39958-1-anup.patel@wdc.com> In-Reply-To: <20210610052221.39958-1-anup.patel@wdc.com> From: Anup Patel Date: Tue, 22 Jun 2021 10:19:11 +0530 Message-ID: Subject: Re: [PATCH v7 0/8] RISC-V CPU Idle Support To: Anup Patel , Palmer Dabbelt , Palmer Dabbelt Cc: Paul Walmsley , Albert Ou , Daniel Lezcano , Ulf Hansson , "Rafael J . Wysocki" , Pavel Machek , Rob Herring , Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , DTML , linux-riscv , "linux-kernel@vger.kernel.org List" , "open list:THERMAL" , linux-arm-kernel Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Palmer, On Thu, Jun 10, 2021 at 10:52 AM Anup Patel wrote: > > This series adds RISC-V CPU Idle support using SBI HSM suspend function. > The RISC-V SBI CPU idle driver added by this series is highly inspired > from the ARM PSCI CPU idle driver. > > At high-level, this series includes the following changes: > 1) Preparatory arch/riscv patches (Patches 1 to 3) > 2) Defines for RISC-V SBI HSM suspend (Patch 4) > 3) Preparatory patch to share code between RISC-V SBI CPU idle driver > and ARM PSCI CPU idle driver (Patch 5) > 4) RISC-V SBI CPU idle driver and related DT bindings (Patches 6 to 7) > > These patches can be found in riscv_sbi_hsm_suspend_v7 branch at > https://github.com/avpatel/linux > > Special thanks Sandeep Tripathy for providing early feeback on SBI HSM > support in all above projects (RISC-V SBI specification, OpenSBI, and > Linux RISC-V). > > Changes since v6: > - Fixed error reported by "make DT_CHECKER_FLAGS=-m dt_binding_check" > > Changes since v5: > - Rebased on Linux-5.13-rc5 > - Removed unnecessary exports from PATCH5 > - Removed stray ";" from PATCH5 > - Moved sbi_cpuidle_pd_power_off() under "#ifdef CONFIG_DT_IDLE_GENPD" > in PATCH6 > > Changes since v4: > - Rebased on Linux-5.13-rc2 > - Renamed all dt_idle_genpd functions to have "dt_idle_" prefix > - Added MAINTAINERS file entry for dt_idle_genpd > > Changes since v3: > - Rebased on Linux-5.13-rc2 > - Fixed __cpu_resume_enter() which was broken due to XIP kernel support > - Removed "struct dt_idle_genpd_ops" abstraction which simplifies code > sharing between ARM PSCI and RISC-V SBI drivers in PATCH5 > > Changes since v2: > - Rebased on Linux-5.12-rc3 > - Updated PATCH7 to add common DT bindings for both ARM and RISC-V > idle states > - Added "additionalProperties = false" for both idle-states node and > child nodes in PATCH7 > > Changes since v1: > - Fixex minor typo in PATCH1 > - Use just "idle-states" as DT node name for CPU idle states > - Added documentation for "cpu-idle-states" DT property in > devicetree/bindings/riscv/cpus.yaml > - Added documentation for "riscv,sbi-suspend-param" DT property in > devicetree/bindings/riscv/idle-states.yaml > > Anup Patel (8): > RISC-V: Enable CPU_IDLE drivers > RISC-V: Rename relocate() and make it global > RISC-V: Add arch functions for non-retentive suspend entry/exit > RISC-V: Add SBI HSM suspend related defines > cpuidle: Factor-out power domain related code from PSCI domain driver > cpuidle: Add RISC-V SBI CPU idle driver > dt-bindings: Add common bindings for ARM and RISC-V idle states > RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU virt machine Can you please review this series ? It would be nice to consider this series for Linux-5.14. Regards, Anup > > .../bindings/arm/msm/qcom,idle-state.txt | 2 +- > .../devicetree/bindings/arm/psci.yaml | 2 +- > .../bindings/{arm => cpu}/idle-states.yaml | 228 ++++++- > .../devicetree/bindings/riscv/cpus.yaml | 6 + > MAINTAINERS | 14 + > arch/riscv/Kconfig | 7 + > arch/riscv/Kconfig.socs | 3 + > arch/riscv/configs/defconfig | 13 +- > arch/riscv/configs/rv32_defconfig | 6 +- > arch/riscv/include/asm/asm.h | 17 + > arch/riscv/include/asm/cpuidle.h | 24 + > arch/riscv/include/asm/sbi.h | 27 +- > arch/riscv/include/asm/suspend.h | 35 + > arch/riscv/kernel/Makefile | 2 + > arch/riscv/kernel/asm-offsets.c | 3 + > arch/riscv/kernel/cpu_ops_sbi.c | 2 +- > arch/riscv/kernel/head.S | 18 +- > arch/riscv/kernel/process.c | 3 +- > arch/riscv/kernel/suspend.c | 86 +++ > arch/riscv/kernel/suspend_entry.S | 123 ++++ > drivers/cpuidle/Kconfig | 9 + > drivers/cpuidle/Kconfig.arm | 1 + > drivers/cpuidle/Kconfig.riscv | 15 + > drivers/cpuidle/Makefile | 5 + > drivers/cpuidle/cpuidle-psci-domain.c | 138 +--- > drivers/cpuidle/cpuidle-psci.h | 15 +- > drivers/cpuidle/cpuidle-sbi.c | 626 ++++++++++++++++++ > drivers/cpuidle/dt_idle_genpd.c | 177 +++++ > drivers/cpuidle/dt_idle_genpd.h | 50 ++ > 29 files changed, 1472 insertions(+), 185 deletions(-) > rename Documentation/devicetree/bindings/{arm => cpu}/idle-states.yaml (74%) > create mode 100644 arch/riscv/include/asm/cpuidle.h > create mode 100644 arch/riscv/include/asm/suspend.h > create mode 100644 arch/riscv/kernel/suspend.c > create mode 100644 arch/riscv/kernel/suspend_entry.S > create mode 100644 drivers/cpuidle/Kconfig.riscv > create mode 100644 drivers/cpuidle/cpuidle-sbi.c > create mode 100644 drivers/cpuidle/dt_idle_genpd.c > create mode 100644 drivers/cpuidle/dt_idle_genpd.h > > -- > 2.25.1 >