From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C14AAC433F5 for ; Wed, 18 May 2022 09:10:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233871AbiERJKi (ORCPT ); Wed, 18 May 2022 05:10:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233816AbiERJKe (ORCPT ); Wed, 18 May 2022 05:10:34 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBA5613FD4B for ; Wed, 18 May 2022 02:10:32 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id e28so1160883wra.10 for ; Wed, 18 May 2022 02:10:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20210112.gappssmtp.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=a3p9RWrnEXxuXT6dFm/7R9XKBCQLFHr/hqKCZKCwClw=; b=fQrjJ1mkMaN1bDs4bljWNln+PTHlRBIcCuDsEtqZI3kxqy/TCbvnab19SOWxPwBcNx Gd7rnjVnpgj4gHHAO8p/VcsKSEl+buT4rUmPNPUDybXMuE1qQoIKtLZmRMEkDDT9xQzZ xNr7HixN/r3XvE8advX4UMeflrvwCBfVFePGyQ5gqD9GcM39OwrJalg+HrVG2m9WNBIx mkDnzf3oO51nkKsaNTKVkEgSFI+8wrf63eAsf4DVyHBpXDJVTFnzbZ/f5KyZHiOR4r9/ Xf5ULHRiVN5DlIVYtHH1ratKRFbWL0ganQ6OYpAJKlj0T7TbGf1GhDneNkhohVMVSgJT vCQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=a3p9RWrnEXxuXT6dFm/7R9XKBCQLFHr/hqKCZKCwClw=; b=dPgr6PoisXde4E+uSHMaSi6y3AURS1srXk1BmlN3icA698IGfUp33HFP/ABwx6ANsW 4kRiQrVUtRjZb8eFWpu0IqXsxs7inIRWokASW76PbgeR9xhURyiql9NjDDS4rxoxByEj GENPQRe6+TKznR6yzM57myHpKLjA07GqBss4ky0k+ebdld/C0njBHHWrxBJ3S1FsAI0S 1Rggi/0oVbnibPjQjcMz7pf4dAFNicGI4ZrHZvz3b1WJl3bnz3tmdor1WwgO82BlnYu0 jBLZFpCektRSS8JFEaTgCNK8r7W5ro+1IdV8HK7AiV+cIwV6rZL8MLiuhSukPLwT3n+C GrOg== X-Gm-Message-State: AOAM53168sG78Te9zXJpasagnmiIQ98ilBE9RXtzp7ced7EHB/+G5bY9 o1GNa2aQ2gSKIGLIkU46AomJ2SvgwzrQZfBC1PR5iQ== X-Google-Smtp-Source: ABdhPJxEBbxF3pXDvjlrj+8J/Mp0IPHVhx92EKQ7mad6xuIFVFaIXgAUqG7xHGRDd0SLlUagfaA23fzfMIzbtsnt99g= X-Received: by 2002:a5d:6c6b:0:b0:1ea:77ea:dde8 with SMTP id r11-20020a5d6c6b000000b001ea77eadde8mr22568351wrz.690.1652865031225; Wed, 18 May 2022 02:10:31 -0700 (PDT) MIME-Version: 1.0 References: <20220511214132.2281431-1-heiko@sntech.de> <20220518002529.GA1928329-robh@kernel.org> <1893094.PYKUYFuaPT@diego> In-Reply-To: <1893094.PYKUYFuaPT@diego> From: Anup Patel Date: Wed, 18 May 2022 14:40:17 +0530 Message-ID: Subject: Re: [PATCH v2 1/3] dt-bindings: riscv: document cbom-block-size To: =?UTF-8?Q?Heiko_St=C3=BCbner?= Cc: Rob Herring , Philipp Tomsich , Palmer Dabbelt , Paul Walmsley , linux-riscv , "linux-kernel@vger.kernel.org List" , Wei Fu , Guo Ren , Atish Patra , Nick Kossifidis , Samuel Holland , Christoph Muellner , krzk+dt@kernel.org, DTML Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, May 18, 2022 at 2:33 PM Heiko St=C3=BCbner wrote: > > Am Mittwoch, 18. Mai 2022, 10:22:17 CEST schrieb Philipp Tomsich: > > +David Kruckemyer (who is chairing the CMO task-group within RVI). > > > > On Wed, 18 May 2022 at 02:25, Rob Herring wrote: > > > > > > On Wed, May 11, 2022 at 11:41:30PM +0200, Heiko Stuebner wrote: > > > > The Zicbom operates on a block-size defined for the cpu-core, > > > > which does not necessarily match other cache-sizes used. > > > > > > > > So add the necessary property for the system to know the core's > > > > block-size. > > > > > > > > Signed-off-by: Heiko Stuebner > > > > --- > > > > Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++ > > > > 1 file changed, 7 insertions(+) > > > > > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Do= cumentation/devicetree/bindings/riscv/cpus.yaml > > > > index d632ac76532e..b179bfd155a3 100644 > > > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > > > @@ -63,6 +63,13 @@ properties: > > > > - riscv,sv48 > > > > - riscv,none > > > > > > > > + riscv,cbom-block-size: > > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > > > > Any value 0-2^32 is valid? > > > > > > > + description: > > > > + Blocksize in bytes for the Zicbom cache operations. The bloc= k > > > > + size is a property of the core itself and does not necessari= ly > > > > + match other software defined cache sizes. > > > > > > What about hardware defined cache sizes? I'm scratching my head as to > > > what a 'software defined cache size' is. > > I agree that this should be worded better. The intent was to tell that th= is > is different from say the l1-cache-block-size. > > I.e. these values can be the same but don't need to be. But I guess I got > too much lead on by a kernel implementation detail (L1_CACHE_BYTES consta= nt) Better to just call it as "the cache block-size expected by Zicbom cache operations" without getting details of relation with L1 cache block size. Regards, Anup > > > > This seems to be a misnomer, as the specification doesn't use the term > > and rather talks about the "size of a cache block for [operation > > name]". > > > > There are currently two such 'operation sizes' discoverable by software= : > > - size of the cache block for management and prefetch instructions > > - size of the cache block for zero instructions > > > > For whatever it's worth, cache operations in RISC-V attempt to > > disassociate the underlying hardware cache geometry from software. > > See https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmob= ase-v1.0.1.pdf > > for the CMO specification, and the discoverable parameters are listed > > in section 2.7. > > > > Philipp. > > > > > > + > > > > riscv,isa: > > > > description: > > > > Identifies the specific RISC-V instruction set architecture > > > > -- > > > > 2.35.1 > > > > > > > > > > > > > >