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Thu, 12 Oct 2023 07:04:38 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20231003035226.1945725-1-apatel@ventanamicro.com> In-Reply-To: From: Anup Patel Date: Thu, 12 Oct 2023 19:34:27 +0530 Message-ID: Subject: Re: [PATCH v3 0/6] KVM RISC-V Conditional Operations To: Palmer Dabbelt , Paolo Bonzini Cc: Atish Patra , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan , Andrew Jones , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Hi Palmer, On Thu, Oct 5, 2023 at 11:35=E2=80=AFAM Anup Patel wr= ote: > > On Tue, Oct 3, 2023 at 9:22=E2=80=AFAM Anup Patel wrote: > > > > This series extends KVM RISC-V to allow Guest/VM discover and use > > conditional operations related ISA extensions (namely XVentanaCondOps > > and Zicond). > > > > To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condo= ps_v1 > > branch at: https://github.com/avpatel/kvmtool.git > > > > These patches are based upon the latest riscv_kvm_queue and can also be > > found in the riscv_kvm_condops_v3 branch at: > > https://github.com/avpatel/linux.git > > > > Changes since v2: > > - Dropped patch1, patch2, and patch5 since these patches don't meet > > the requirements of patch acceptance policy. > > > > Changes since v1: > > - Rebased the series on riscv_kvm_queue > > - Split PATCH1 and PATCH2 of v1 series into two patches > > - Added separate test configs for XVentanaCondOps and Zicond in PATCH7 > > of v1 series. > > > > Anup Patel (6): > > dt-bindings: riscv: Add Zicond extension entry > > RISC-V: Detect Zicond from ISA string > > RISC-V: KVM: Allow Zicond extension for Guest/VM > > KVM: riscv: selftests: Add senvcfg register to get-reg-list test > > KVM: riscv: selftests: Add smstateen registers to get-reg-list test > > KVM: riscv: selftests: Add condops extensions to get-reg-list test > > Queued this series for Linux-6.7 I have created shared tag kvm-riscv-shared-tag-6.7 in the KVM RISC-V repo at: https://github.com/kvm-riscv/linux.git This shared tag is based on 6.6-rc5 and contains following 4 patches: dt-bindings: riscv: Add Zicond extension entry RISC-V: Detect Zicond from ISA string dt-bindings: riscv: Add smstateen entry RISC-V: Detect Smstateen extension Thanks, Anup > > Thanks, > Anup > > > > > .../devicetree/bindings/riscv/extensions.yaml | 6 +++ > > arch/riscv/include/asm/hwcap.h | 1 + > > arch/riscv/include/uapi/asm/kvm.h | 1 + > > arch/riscv/kernel/cpufeature.c | 1 + > > arch/riscv/kvm/vcpu_onereg.c | 2 + > > .../selftests/kvm/riscv/get-reg-list.c | 54 +++++++++++++++++++ > > 6 files changed, 65 insertions(+) > > > > -- > > 2.34.1 > >