From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDA94C433EF for ; Tue, 8 Feb 2022 08:54:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352229AbiBHIyT (ORCPT ); Tue, 8 Feb 2022 03:54:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352175AbiBHIyS (ORCPT ); Tue, 8 Feb 2022 03:54:18 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1AAAC03FEC1 for ; Tue, 8 Feb 2022 00:54:17 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id h6so10655521wrb.9 for ; Tue, 08 Feb 2022 00:54:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20210112.gappssmtp.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ad/AIeKw/gggP6Br2uoykBbNKFVMSxSNAtQyiBt1RW0=; b=5KxMGJIrZxz0UdJJ4KFG3h5rV0PZviBM1D2ZlImvgl2AYSR7uVDIp9FOmugYxXR0jd /uG/+J603tKg3P37pGqHHlbr3fFTWLeZiT1w6+erAhedOqoJk8L3BOwALYuFUkgt9rFv jQiGMsXhV5QujyODOTCAMmYW8e/ggOnHL5d6jTVn1If8szV5+b8LHzdFdowkrSUMEWah jPTmEQXdKOuovazsDjAlCKdIyJVrK45UjaRmuw4mwTheKA34Yrm9QDVifKZ9hcVLF1Go vZJYetHiq9fRPxQVsdpQnn9p5KE/Ol1buMRKZZWhAVmq4hbRovF1sdC/5fDZhn2tpOSm 5hLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ad/AIeKw/gggP6Br2uoykBbNKFVMSxSNAtQyiBt1RW0=; b=kH8gImpwtvBXHkyIYlplsVelT2DvMAE+8hTUxyHYT0fP/5+Pua2uEOQ4LvpD+MIz+0 YUgkCLklCc6DzTg2dzqNGTygIFsYoHlpHbeZrFvaw0+As5IanQVT9DT86AJ7PFq8n/pT dlihY+WnjMxDne/WdKfWn3UUF5R7oy88hSDlHJSoa9PUWLRHDbTKbaGRfbUIhhtQBnxK Mv+8Aue38nr5sVJLS77CjhYB2CGHqy2Ncz9aPriPfHXByif+Z05013Kl3cNNU+uqJvBn 4YkOHQow+8WFpoB3Mn9n9EWgMccG3wQm9A9kRGh6QbX3PEAMPhHB5uq3kQO2HAWWVMBp 2uKA== X-Gm-Message-State: AOAM5310XevB7UBtNtw/2vvcdtwKPvALxuGmvmHDYybmKsDRnTpMC1Dv JNLyGEEUDfqN2BjPBh15DDcnwt9jgNcj2Dm1CCH7IA== X-Google-Smtp-Source: ABdhPJzgSop4y+Hsg6mK+sVfvqbbliyC19eTL7sLF/m+UVhe/JN/7WOPjVFLYB6Xxfkqx+mpiM4ybuPoWNgcPTqKJbA= X-Received: by 2002:adf:bc44:: with SMTP id a4mr2655518wrh.346.1644310456139; Tue, 08 Feb 2022 00:54:16 -0800 (PST) MIME-Version: 1.0 References: <20220126114452.692512-1-apatel@ventanamicro.com> <20220126114452.692512-9-apatel@ventanamicro.com> In-Reply-To: From: Anup Patel Date: Tue, 8 Feb 2022 14:24:04 +0530 Message-ID: Subject: Re: [PATCH v10 8/8] RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU virt machine To: Guo Ren Cc: Anup Patel , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Ulf Hansson , "Rafael J . Wysocki" , Pavel Machek , Rob Herring , Sandeep Tripathy , Atish Patra , Alistair Francis , Liush , devicetree , linux-riscv , Linux Kernel Mailing List , "open list:THERMAL" , Linux ARM , kvm-riscv@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, Feb 8, 2022 at 12:16 PM Guo Ren wrote: > > Another question: > > Have you put "idle-states {" in qemu's DTS? or how do you test your patches? I usually do the following: 1) Dump QEMU virt machine DTB 2) Convert QEMU virt machine DTB into DTS 3) Add "idle-states" in QEMU virt machine DTS 4) Create QEMU virt machine DTB with "idle-states" 5) Use the new QEMU virt machine DTB for testing this series. Here's one of the DTS files which I used for testing on QEMU virt machine: /dts-v1/; / { #address-cells = <0x02>; #size-cells = <0x02>; compatible = "riscv-virtio"; model = "riscv-virtio,qemu"; chosen { linux,initrd-end = <0x8855d200>; linux,initrd-start = <0x88200000>; bootargs = "root=/dev/ram rw console=ttyS0 earlycon"; stdout-path = "/soc/uart@10000000"; }; memory@80000000 { device_type = "memory"; reg = <0x00 0x80000000 0x00 0x10000000>; }; cpus { #address-cells = <0x01>; #size-cells = <0x00>; timebase-frequency = <0x989680>; cpu@0 { phandle = <0x07>; device_type = "cpu"; reg = <0x00>; status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafdcsu"; mmu-type = "riscv,sv48"; cpu-idle-states = <&CPU_NONRET_DEF>; interrupt-controller { #interrupt-cells = <0x01>; interrupt-controller; compatible = "riscv,cpu-intc"; phandle = <0x08>; }; }; cpu@1 { phandle = <0x05>; device_type = "cpu"; reg = <0x01>; status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafdcsu"; mmu-type = "riscv,sv48"; cpu-idle-states = <&CPU_RET_DEF>; interrupt-controller { #interrupt-cells = <0x01>; interrupt-controller; compatible = "riscv,cpu-intc"; phandle = <0x06>; }; }; cpu@2 { phandle = <0x03>; device_type = "cpu"; reg = <0x02>; status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafdcsu"; mmu-type = "riscv,sv48"; cpu-idle-states = <&CPU_NONRET_DEF>; interrupt-controller { #interrupt-cells = <0x01>; interrupt-controller; compatible = "riscv,cpu-intc"; phandle = <0x04>; }; }; cpu@3 { phandle = <0x01>; device_type = "cpu"; reg = <0x03>; status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafdcsu"; mmu-type = "riscv,sv48"; cpu-idle-states = <&CPU_RET_DEF>; interrupt-controller { #interrupt-cells = <0x01>; interrupt-controller; compatible = "riscv,cpu-intc"; phandle = <0x02>; }; }; cpu-map { cluster0 { core0 { cpu = <0x07>; }; core1 { cpu = <0x05>; }; core2 { cpu = <0x03>; }; core3 { cpu = <0x01>; }; }; }; idle-states { CPU_RET_DEF: cpu-retentive-default { compatible = "riscv,idle-state"; riscv,sbi-suspend-param = <0x00000000>; entry-latency-us = <10>; exit-latency-us = <10>; min-residency-us = <100>; }; CPU_NONRET_DEF: cpu-nonretentive-default { compatible = "riscv,idle-state"; riscv,sbi-suspend-param = <0x80000000>; entry-latency-us = <100>; exit-latency-us = <100>; min-residency-us = <1000>; }; }; }; soc { #address-cells = <0x02>; #size-cells = <0x02>; compatible = "simple-bus"; ranges; flash@20000000 { bank-width = <0x04>; reg = <0x00 0x20000000 0x00 0x2000000 0x00 0x22000000 0x00 0x2000000>; compatible = "cfi-flash"; }; rtc@101000 { interrupts = <0x0b>; interrupt-parent = <0x09>; reg = <0x00 0x101000 0x00 0x1000>; compatible = "google,goldfish-rtc"; }; uart@10000000 { interrupts = <0x0a>; interrupt-parent = <0x09>; clock-frequency = <0x384000>; reg = <0x00 0x10000000 0x00 0x100>; compatible = "ns16550a"; }; poweroff { value = <0x5555>; offset = <0x00>; regmap = <0x0a>; compatible = "syscon-poweroff"; }; reboot { value = <0x7777>; offset = <0x00>; regmap = <0x0a>; compatible = "syscon-reboot"; }; test@100000 { phandle = <0x0a>; reg = <0x00 0x100000 0x00 0x1000>; compatible = "sifive,test1\0sifive,test0\0syscon"; }; pci@30000000 { interrupt-map-mask = <0x1800 0x00 0x00 0x07>; interrupt-map = <0x00 0x00 0x00 0x01 0x09 0x20 0x00 0x00 0x00 0x02 0x09 0x21 0x00 0x00 0x00 0x03 0x09 0x22 0x00 0x00 0x00 0x04 0x09 0x23 0x800 0x00 0x00 0x01 0x09 0x21 0x800 0x00 0x00 0x02 0x09 0x22 0x800 0x00 0x00 0x03 0x09 0x23 0x800 0x00 0x00 0x04 0x09 0x20 0x1000 0x00 0x00 0x01 0x09 0x22 0x1000 0x00 0x00 0x02 0x09 0x23 0x1000 0x00 0x00 0x03 0x09 0x20 0x1000 0x00 0x00 0x04 0x09 0x21 0x1800 0x00 0x00 0x01 0x09 0x23 0x1800 0x00 0x00 0x02 0x09 0x20 0x1800 0x00 0x00 0x03 0x09 0x21 0x1800 0x00 0x00 0x04 0x09 0x22>; ranges = <0x1000000 0x00 0x00 0x00 0x3000000 0x00 0x10000 0x2000000 0x00 0x40000000 0x00 0x40000000 0x00 0x40000000>; reg = <0x00 0x30000000 0x00 0x10000000>; dma-coherent; bus-range = <0x00 0xff>; linux,pci-domain = <0x00>; device_type = "pci"; compatible = "pci-host-ecam-generic"; #size-cells = <0x02>; #interrupt-cells = <0x01>; #address-cells = <0x03>; }; virtio_mmio@10008000 { interrupts = <0x08>; interrupt-parent = <0x09>; reg = <0x00 0x10008000 0x00 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@10007000 { interrupts = <0x07>; interrupt-parent = <0x09>; reg = <0x00 0x10007000 0x00 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@10006000 { interrupts = <0x06>; interrupt-parent = <0x09>; reg = <0x00 0x10006000 0x00 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@10005000 { interrupts = <0x05>; interrupt-parent = <0x09>; reg = <0x00 0x10005000 0x00 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@10004000 { interrupts = <0x04>; interrupt-parent = <0x09>; reg = <0x00 0x10004000 0x00 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@10003000 { interrupts = <0x03>; interrupt-parent = <0x09>; reg = <0x00 0x10003000 0x00 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@10002000 { interrupts = <0x02>; interrupt-parent = <0x09>; reg = <0x00 0x10002000 0x00 0x1000>; compatible = "virtio,mmio"; }; virtio_mmio@10001000 { interrupts = <0x01>; interrupt-parent = <0x09>; reg = <0x00 0x10001000 0x00 0x1000>; compatible = "virtio,mmio"; }; plic@c000000 { phandle = <0x09>; riscv,ndev = <0x35>; reg = <0x00 0xc000000 0x00 0x210000>; interrupts-extended = <0x08 0x0b 0x08 0x09 0x06 0x0b 0x06 0x09 0x04 0x0b 0x04 0x09 0x02 0x0b 0x02 0x09>; interrupt-controller; compatible = "riscv,plic0"; #interrupt-cells = <0x01>; #address-cells = <0x00>; }; clint@2000000 { interrupts-extended = <0x08 0x03 0x08 0x07 0x06 0x03 0x06 0x07 0x04 0x03 0x04 0x07 0x02 0x03 0x02 0x07>; reg = <0x00 0x2000000 0x00 0x10000>; compatible = "riscv,clint0"; }; }; }; Regards, Anup