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AJvYcCWpkuwaYqHfQCWJmxxDXdm3qFkXuLAa0f19R/e+ReaB5pAknTOk6H+zDU3ZSa9CUnALAXYAcm2Smmz7QzSgssk8zKhs6u5QjK5+yQ== X-Gm-Message-State: AOJu0YwvrMaVi/RpouNeensur9XwyC46CkXRtsZRUr7t+a4kZ+0XfP1c 9risYv6w0M8e3PB48ov57Y66Q3hmV6BmkYfulpJux3QLNJgw7u1ukb5iYksLc7EwdxbcLFoN9+R HLc6CW56LyJL/80yitM9GrrOuYoYt3bwzH7q1QuS8A+inQ/+z X-Google-Smtp-Source: AGHT+IH7+5ZCczA7CU0C46qlCuTGH9ZfX4fnyGxuO1KETodyAdfp/RwxJf4awEiJMnqjcwJ7wcD82uB7iK3DMxQoA9s= X-Received: by 2002:a05:6e02:1292:b0:363:da36:f643 with SMTP id y18-20020a056e02129200b00363da36f643mr18895064ilq.8.1708608637266; Thu, 22 Feb 2024 05:30:37 -0800 (PST) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240222094006.1030709-1-apatel@ventanamicro.com> <20240222094006.1030709-14-apatel@ventanamicro.com> <87msrstzck.fsf@all.your.base.are.belong.to.us> In-Reply-To: <87msrstzck.fsf@all.your.base.are.belong.to.us> From: Anup Patel Date: Thu, 22 Feb 2024 19:00:25 +0530 Message-ID: Subject: Re: [PATCH v14 13/18] irqchip/riscv-imsic: Add device MSI domain support for PCI devices To: =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= Cc: Anup Patel , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley , devicetree@vger.kernel.org, Saravana Kannan , Marc Zyngier , linux-kernel@vger.kernel.org, Atish Patra , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Andrew Jones Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Feb 22, 2024 at 6:44=E2=80=AFPM Bj=C3=B6rn T=C3=B6pel wrote: > > Anup Patel writes: > > > The Linux PCI framework supports per-device MSI domains for PCI devices > > so extend the IMSIC driver to allow PCI per-device MSI domains. > > > > Signed-off-by: Anup Patel > > --- > > drivers/irqchip/Kconfig | 7 +++++ > > drivers/irqchip/irq-riscv-imsic-platform.c | 35 ++++++++++++++++++++-- > > 2 files changed, 40 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig > > index 85f86e31c996..2fc0cb32341a 100644 > > --- a/drivers/irqchip/Kconfig > > +++ b/drivers/irqchip/Kconfig > > @@ -553,6 +553,13 @@ config RISCV_IMSIC > > select GENERIC_IRQ_MATRIX_ALLOCATOR > > select GENERIC_MSI_IRQ > > > > +config RISCV_IMSIC_PCI > > + bool > > + depends on RISCV_IMSIC > > + depends on PCI > > + depends on PCI_MSI > > + default RISCV_IMSIC > > + > > config EXYNOS_IRQ_COMBINER > > bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST > > depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST > > diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqch= ip/irq-riscv-imsic-platform.c > > index e2344fc08dca..90ddcdd0bba5 100644 > > --- a/drivers/irqchip/irq-riscv-imsic-platform.c > > +++ b/drivers/irqchip/irq-riscv-imsic-platform.c > > @@ -14,6 +14,7 @@ > > #include > > #include > > #include > > +#include > > #include > > #include > > #include > > @@ -208,6 +209,28 @@ static const struct irq_domain_ops imsic_base_doma= in_ops =3D { > > #endif > > }; > > > > +#ifdef CONFIG_RISCV_IMSIC_PCI > > + > > +static void imsic_pci_mask_irq(struct irq_data *d) > > +{ > > + pci_msi_mask_irq(d); > > + irq_chip_mask_parent(d); > > +} > > + > > +static void imsic_pci_unmask_irq(struct irq_data *d) > > +{ > > + irq_chip_unmask_parent(d); > > + pci_msi_unmask_irq(d); > > +} > > + > > +#define MATCH_PCI_MSI BIT(DOMAIN_BUS_PCI_MSI) > > + > > +#else > > + > > +#define MATCH_PCI_MSI 0 > > + > > +#endif > > + > > static bool imsic_init_dev_msi_info(struct device *dev, > > struct irq_domain *domain, > > struct irq_domain *real_parent, > > @@ -231,6 +254,13 @@ static bool imsic_init_dev_msi_info(struct device = *dev, > > > > /* Is the target supported? */ > > switch (info->bus_token) { > > +#ifdef CONFIG_RISCV_IMSIC_PCI > > + case DOMAIN_BUS_PCI_DEVICE_MSI: > > + case DOMAIN_BUS_PCI_DEVICE_MSIX: > > + info->chip->irq_mask =3D imsic_pci_mask_irq; > > + info->chip->irq_unmask =3D imsic_pci_unmask_irq; > > irq_set_affinity()? It's already set by the switch-case above. Regards, Anup