From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33813C61DA4 for ; Thu, 2 Feb 2023 12:55:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232067AbjBBMz1 (ORCPT ); Thu, 2 Feb 2023 07:55:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232089AbjBBMzV (ORCPT ); Thu, 2 Feb 2023 07:55:21 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EDDBA8AC11 for ; Thu, 2 Feb 2023 04:55:09 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id j17so2843712lfr.3 for ; Thu, 02 Feb 2023 04:55:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=p0OggBaEVM084sMCW8HBWOrUa7UEjlo8LtE+1sylal4=; b=wMflCs4LRrR6rx0v5FUohA45XpEpxNpUO82rPsPLRH/jXDhlIwsosRKYSnnLSjfisK fI/DEgEyzseoBqcbf32s22RhlWE8jJAnWYL7dAXc7BvCrm3PouFpS1sS9TQsHE23wpBI BFrG3dVV0Iyo2S1xUHRj6rrjfIVSNHfiQhvYHJURC102lItPydI+18WNfObcViw6zGIr dCcl0osS0YaevOaR/UsGDBbfP5ZWN1ClX3oS7raXmTATGdHvomOR9P+LktGumcknhvvd H33l5FmbJWokijfLdjLWu/B2hXZ3fneak/KwX0OmqgM0OC736TEucbKOESx6S326gHXe 6KGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p0OggBaEVM084sMCW8HBWOrUa7UEjlo8LtE+1sylal4=; b=lQzQ8npwc8BrbVjH47YpkNFYq8Xwc1KXSbyAJqvbQjruoYFAwvUfHmvhLHQXp3vcDr QR4KTyO/Ad7I047/mZIS74M3MBu7N3jfzaIYtO0dKT3NYxU7xxPC2y9FBla9n0FD9pxT xwEUzdUm+TTIGO59BaXVu09JiJKRCXCFX86IEfzRp1SxugBDvPvkyne2/y5eTipqWJYS 1knxD91t246ETvfev5KhLNN32tq7dAmONkoiIUKeOQlhy0zXSwg5wsp1QF8lsg+i5GVR 3/uFc3bM83KUNG9FV1qhIQTME/bvsGsJTOSuGD98VDXg35EWpF/pvlOpnkrYMsoD5zVb +fRQ== X-Gm-Message-State: AO0yUKVWrK1UsFZyTTJ2VqAkKUs3PBqyH9oTc+CY06wRDKiqSAAh2yar Q+eqWrqinIYXOOMdwIrDLHL8oBLkhgczC5GQ5vutOw== X-Google-Smtp-Source: AK7set/mWmeaWd2wkMNBFXbA51O652xW98OUEb1CzsuGrHbl8sBzDY3nLrJoIabdvmMj4YTWwXKt7B5+qymwtAEVesA= X-Received: by 2002:a05:6512:3d28:b0:4d8:8ad1:a05c with SMTP id d40-20020a0565123d2800b004d88ad1a05cmr836274lfv.140.1675342508144; Thu, 02 Feb 2023 04:55:08 -0800 (PST) MIME-Version: 1.0 References: <20230201080227.473547-1-jun.nie@linaro.org> <20230201080227.473547-2-jun.nie@linaro.org> <515f4e9e-2804-e03a-26f5-f2d3ac331109@linaro.org> <71ba0d05-6183-95ef-9e45-cc3dd512475f@linaro.org> In-Reply-To: From: Jun Nie Date: Thu, 2 Feb 2023 20:55:04 +0800 Message-ID: Subject: Re: [PATCH 2/2] PM / devfreq: qcom: Introduce CCI devfreq driver To: Dmitry Baryshkov Cc: "Bryan O'Donoghue" , myungjoo.ham@samsung.com, kyungmin.park@samsung.com, cw00.choi@samsung.com, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Dmitry Baryshkov =E4=BA=8E2023=E5=B9=B42=E6= =9C=881=E6=97=A5=E5=91=A8=E4=B8=89 21:41=E5=86=99=E9=81=93=EF=BC=9A > > On Wed, 1 Feb 2023 at 13:46, Bryan O'Donoghue > wrote: > > > > On 01/02/2023 11:32, Dmitry Baryshkov wrote: > > > On 01/02/2023 10:02, Jun Nie wrote: > > >> Cache Coherent Interconnect (CCI) is used by some Qualcomm SoCs. Thi= s > > >> driver is introduced so that its freqency can be adjusted. And regul= ator > > >> associated with opp table can be also adjusted accordingly which is > > >> shared with cpu cluster. > > >> > > >> Signed-off-by: Jun Nie > > >> --- > > >> drivers/devfreq/Kconfig | 9 +++ > > >> drivers/devfreq/Makefile | 1 + > > >> drivers/devfreq/qcom-cci.c | 162 +++++++++++++++++++++++++++++++++= ++++ > > >> 3 files changed, 172 insertions(+) > > >> create mode 100644 drivers/devfreq/qcom-cci.c > > > > > > Could you please describe in some additional details what are you try= ing > > > to achieve? Should the CCI frequency be scaled manually or does it > > > follow the cluster frequency? Do clusters vote on the CCI frequency? > > > > > > I'm inclined to ask if it is possible to shift this to the cpufreq OP= P > > > tables? > > > > > > > Might not be so easy to just append CCI opps to the cluster frequency o= pps > > > > cci_cache: qcom,cci { > > compatible =3D "qcom,msm8939-cci"; > > clock-names =3D "devfreq_clk"; > > clocks =3D <&apcs2>; > > governor =3D "cpufreq"; > > operating-points-v2 =3D <&cci_opp_table>; > > power-domains =3D <&cpr>; > > power-domain-names =3D "cpr"; > > nvmem-cells =3D <&cpr_efuse_speedbin_pvs>; > > nvmem-cell-names =3D "cpr_efuse_speedbin_pvs"; > > }; > > > > devfreq-cpufreq { > > cci-cpufreq { > > target-dev =3D <&cci_cache>; > > cpu-to-dev-map-0 =3D > > < 200000 200000000 >, > > < 345600 200000000 >, > > < 400000 200000000 >, > > < 533330 297600000 >, > > < 800000 297600000 >, > > < 960000 297600000 >, > > < 1113600 297000000 >, > > < 1344000 595200000 >, > > < 1459200 595200000 >, > > < 1497600 595200000 >, > > < 1651200 595200000 >; > > cpu-to-dev-map-4 =3D > > < 200000 200000000 >, > > < 249600 200000000 >, > > < 499200 297600000 >, > > < 800000 297600000 >, > > < 998400 595200000 >, > > < 1113600 595200000 >; > > These should map to existing opp entries. > > I ended up doing the interconnect driver that maps a clock to the > interconnect. Then I can use it in the cpu opp tables. > > > }; > > }; > > > > cci_opp_table: cci-opp-table { > > compatible =3D "operating-points-v2"; > > > > opp-200000000 { > > opp-hz =3D /bits/ 64 <200000000>; > > opp-supported-hw =3D <0x3f>; > > required-opps =3D <&cpr_opp3>; > > And these should probably map to max(cpu's CPR opp, CCI's CPR opp). The plan is opp framework to handle it when CPU opp requires both cpr power domain opp and CCI opp. While CCI opp will also requires specific cpr opp. Because= CPU have a opp match table per pvs/speed, while CCI has another match table, it seems impossible to write the cpr opp requirements in the code statically. > > > }; > > > > opp-297600000 { > > opp-hz =3D /bits/ 64 <297600000>; > > opp-supported-hw =3D <0x3f>; > > required-opps =3D <&cpr_opp12>; > > }; > > > > opp-400000000-cpr14 { > > opp-hz =3D /bits/ 64 <400000000>; > > opp-supported-hw =3D <0x1>; > > required-opps =3D <&cpr_opp14>; > > }; > > > > opp-400000000-cpr15 { > > opp-hz =3D /bits/ 64 <400000000>; > > opp-supported-hw =3D <0x3e>; > > required-opps =3D <&cpr_opp15>; > > }; > > > > opp-595200000 { > > opp-hz =3D /bits/ 64 <595200000>; > > opp-supported-hw =3D <0x3f>; > > required-opps =3D <&cpr_opp17>; > > }; > > }; > > > > > > cpr_opp_table: cpr-opp-table { > > compatible =3D "operating-points-v2-qcom-level"; > > > > cpr_opp1: opp1 { > > opp-hz =3D /bits/ 64 <200000000>; > > opp-level =3D <1>; > > qcom,opp-fuse-level =3D <1>; > > }; > > cpr_opp2: opp2 { > > opp-hz =3D /bits/ 64 <345600000>; > > opp-level =3D <2>; > > qcom,opp-fuse-level =3D <1>; > > }; > > cpr_opp3: opp3 { > > opp-hz =3D /bits/ 64 <400000000>; > > opp-level =3D <3>; > > qcom,opp-fuse-level =3D <1>; > > }; > > cpr_opp4: opp4 { > > opp-hz =3D /bits/ 64 <422400000>; > > opp-level =3D <4>; > > qcom,opp-fuse-level =3D <2>; > > }; > > cpr_opp5: opp5 { > > opp-hz =3D /bits/ 64 <499200000>; > > opp-level =3D <5>; > > qcom,opp-fuse-level =3D <2>; > > }; > > cpr_opp6: opp6 { > > opp-hz =3D /bits/ 64 <533330000>; > > opp-level =3D <6>; > > qcom,opp-fuse-level =3D <2>; > > }; > > cpr_opp7: opp7 { > > opp-hz =3D /bits/ 64 <652800000>; > > opp-level =3D <7>; > > qcom,opp-fuse-level =3D <2>; > > }; > > cpr_opp8: opp8 { > > opp-hz =3D /bits/ 64 <729600000>; > > opp-level =3D <8>; > > qcom,opp-fuse-level =3D <2>; > > }; > > cpr_opp9: opp9 { > > opp-hz =3D /bits/ 64 <800000000>; > > opp-level =3D <9>; > > qcom,opp-fuse-level =3D <2>; > > }; > > cpr_opp10: opp10 { > > opp-hz =3D /bits/ 64 <806400000>; > > opp-level =3D <10>; > > qcom,opp-fuse-level =3D <2>; > > }; > > cpr_opp11: opp11 { > > opp-hz =3D /bits/ 64 <883200000>; > > opp-level =3D <11>; > > qcom,opp-fuse-level =3D <2>; > > }; > > cpr_opp12: opp12 { > > opp-hz =3D /bits/ 64 <960000000>; > > opp-level =3D <12>; > > qcom,opp-fuse-level =3D <2>; > > }; > > }; > > > > --- > > bod > > > > -- > With best wishes > Dmitry