From: Legale Legale <legale.legale@gmail.com>
To: "Bryan O'Donoghue" <bryan.odonoghue@linaro.org>
Cc: agross@kernel.org, andersson@kernel.org,
konrad.dybcio@linaro.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: ipq6018: add QUP5 I2C node
Date: Wed, 15 Nov 2023 17:20:33 +0300 [thread overview]
Message-ID: <CACDmYycHgu8JKjRM6xrMeNkruEHMba+afXtSqLq5TCw3y-b0Zw@mail.gmail.com> (raw)
In-Reply-To: <CACDmYyeBbGVPxLh+dmWus=BEiM6rp-1Qn17_RhSyDywrWf8uLw@mail.gmail.com>
Wrong file. sorry. This one is correct:
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index e59b9df96..00a61de9d 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -506,6 +506,21 @@ blsp1_i2c3: i2c@78b7000 {
dma-names = "tx", "rx";
status = "disabled";
};
+
+ blsp1_i2c6: i2c@78ba000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x078ba000 0x0 0x600>;
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ clock-frequency = <400000>;
+ dmas = <&blsp_dma 22>, <&blsp_dma 23>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
qpic_bam: dma-controller@7984000 {
compatible = "qcom,bam-v1.7.0";
--
2.42.0
On Wed, 15 Nov 2023 at 17:18, Legale Legale <legale.legale@gmail.com> wrote:
>
> update again:
>
> ---
> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index e59b9df96..822ac51a0 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -506,6 +506,21 @@ blsp1_i2c3: i2c@78b7000 {
> dma-names = "tx", "rx";
> status = "disabled";
> };
> +
> + blsp1_i2c6: i2c@78ba000 {
> + compatible = "qcom,i2c-qup-v2.2.1";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x078ba000 0x600>;
> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + clock-frequency = <400000>;
> + dmas = <&blsp_dma 22>, <&blsp_dma 23>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
>
> qpic_bam: dma-controller@7984000 {
> compatible = "qcom,bam-v1.7.0";
> --
> 2.42.0
>
> On Wed, 15 Nov 2023 at 17:16, Bryan O'Donoghue
> <bryan.odonoghue@linaro.org> wrote:
> >
> > On 15/11/2023 13:58, Legale Legale wrote:
> > > + reg = <0x078ba000 0x600>;
> >
> > This still doesn't look right.
> >
> > ---
> > bod
next prev parent reply other threads:[~2023-11-15 14:20 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-15 9:55 [PATCH] arm64: dts: qcom: ipq6018: add QUP5 I2C node Legale Legale
2023-11-15 11:32 ` Bryan O'Donoghue
2023-11-15 13:58 ` Legale Legale
2023-11-15 14:16 ` Bryan O'Donoghue
2023-11-15 14:18 ` Legale Legale
2023-11-15 14:20 ` Legale Legale [this message]
2023-11-15 14:28 ` Bryan O'Donoghue
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