From: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
To: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Benjamin Herrenschmidt
<benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org>,
Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>,
Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>,
Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>,
"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
Jeremy Kerr <jk-mnsaURCQ41sdnm+yROfE0A@public.gmane.org>,
Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>,
Baruch Siach <baruch-NswTu9S1W3P6gbPvEgmw2w@public.gmane.org>
Subject: Re: [PATCH v2 1/2] doc/devicetree: Add Aspeed VIC bindings
Date: Wed, 18 May 2016 23:20:31 +0930 [thread overview]
Message-ID: <CACPK8Xe6TDdV3dC=gizXLxLjUziDFhsupUbXSuYsn6bcrAxahQ@mail.gmail.com> (raw)
In-Reply-To: <CAL_JsqJDGmvDxm1kN1w6NQZs0JLeA-V=X_BWi=VOaMTwftLn-w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Fri, May 13, 2016 at 2:50 AM, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Wed, May 11, 2016 at 8:01 PM, Benjamin Herrenschmidt
> <benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org> wrote:
>> On Wed, 2016-05-11 at 09:33 -0500, Rob Herring wrote:
>>> > +- interrupt-controller : Identifies the node as an interrupt controller
>>> > +- #interrupt-cells : Specifies the number of cells needed to encode an
>>> > + interrupt source. The value shall be 1.
>>>
>>> No need for level vs. edge flags?
>>
>> That's an open question. Most interrupts are fixed. A handful of GPIOs
>> can be configured either way. For now I am relying on uboot setting up
>> the right config for them and I read it back at boot time, but we could
>> make it part of the binding I suppose.
>
> It is almost standard to just use 2 cells here even if reserved for
> future use. Especially since the IP block seems to have registers to
> control that.
Yep, makes sense. I've added this to the bindings document.
I was trying to use the second cell in our driver:
static struct irq_domain_ops avic_dom_ops = {
.map = avic_map,
.xlate = irq_domain_xlate_twocell,
};
So we have irq_domain_xlate_twocell to parse the device tree and
grabs the type property from the second cell.
In avic_map we set the irq handler:
if (vic->edge_sources[sidx] & sbit) {
/* TODO: Check aginst type from dt and warn if not edge */
irq_set_chip_and_handler(irq, &avic_chip, handle_edge_irq);
} else {
/* TODO: Check aginst type from dt and warn if not level */
irq_set_chip_and_handler(irq, &avic_chip, handle_level_irq);
}
However, we don't have the type here, so we can't use it to check that
we're setting the correct edge/level callback (or use it to set the
register in the future if we want to use the device tree to override
the bootloader settings).
I had a look at some other drivers and they don't seem to use the dt
property when mapping the irq. What am I missing here?
Cheers,
Joel
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next prev parent reply other threads:[~2016-05-18 13:50 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <462797239-14765-1-git-send-email-joel@jms.id.au>
2016-05-09 13:58 ` [PATCH v2 0/2] irqchip: Support Aspeed IRQ controller Joel Stanley
2016-05-09 13:58 ` [PATCH v2 1/2] doc/devicetree: Add Aspeed VIC bindings Joel Stanley
[not found] ` <1462802317-27086-2-git-send-email-joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
2016-05-11 14:33 ` Rob Herring
2016-05-12 1:01 ` Benjamin Herrenschmidt
[not found] ` <1463014882.20290.203.camel-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org>
2016-05-12 17:20 ` Rob Herring
[not found] ` <CAL_JsqJDGmvDxm1kN1w6NQZs0JLeA-V=X_BWi=VOaMTwftLn-w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-05-18 13:50 ` Joel Stanley [this message]
[not found] ` <CACPK8Xe6TDdV3dC=gizXLxLjUziDFhsupUbXSuYsn6bcrAxahQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-05-20 20:13 ` Rob Herring
[not found] ` <1462802317-27086-1-git-send-email-joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
2016-05-09 13:58 ` [PATCH v2 2/2] irqchip: Add irq controller for Aspeed Joel Stanley
2016-05-12 14:43 ` [PATCH v3 0/2] irqchip: Support Aspeed IRQ controller Joel Stanley
[not found] ` <1463064193-2178-1-git-send-email-joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
2016-05-12 14:43 ` [PATCH v3 1/2] doc/devicetree: Add Aspeed VIC bindings Joel Stanley
2016-05-12 14:43 ` [PATCH v3 2/2] irqchip: Add irq controller for Aspeed Joel Stanley
2016-06-22 18:53 ` [PATCH v3 0/2] irqchip: Support Aspeed IRQ controller Jason Cooper
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