From: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
To: "Cédric Le Goater" <clg-Bxea+6Xhats@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH 1/2] ARM: dts: aspeed: add SPI controller bindings
Date: Mon, 6 Mar 2017 09:43:45 +1030 [thread overview]
Message-ID: <CACPK8XeaSh8MVTfPjwt=+NBPWCkMK7QqpAXF7+BYYQBViVSNKg@mail.gmail.com> (raw)
In-Reply-To: <1488378403-24640-2-git-send-email-clg-Bxea+6Xhats@public.gmane.org>
Hi Cedric,
On Thu, Mar 2, 2017 at 12:56 AM, Cédric Le Goater <clg-Bxea+6Xhats@public.gmane.org> wrote:
> Let's define the SPI controllers in the Aspeed SoCs AST2500 and
> AST2400 and also enable these, as well as the chips, on the associated
> platforms.
Thanks for this. Was there a reason you didn't modify the romulus dts as well?
Cheers,
Joel
>
> Signed-off-by: Cédric Le Goater <clg-Bxea+6Xhats@public.gmane.org>
> ---
> arch/arm/boot/dts/aspeed-ast2500-evb.dts | 20 +++++++++
> arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 16 +++++++
> arch/arm/boot/dts/aspeed-g4.dtsi | 29 ++++++++++++
> arch/arm/boot/dts/aspeed-g5.dtsi | 63 +++++++++++++++++++++++++++
> 4 files changed, 128 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
> index d967603dade8..8f82e8ab1875 100644
> --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts
> +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
> @@ -20,6 +20,26 @@
> };
> };
>
> +&fmc {
> + status = "okay";
> + flash@0 {
> + status = "okay";
> + label = "bmc";
> + };
> +};
> +
> +&spi1 {
> + status = "okay";
> + flash@0 {
> + status = "okay";
> + label = "pnor";
> + };
> +};
> +
> +&spi2 {
> + status = "okay";
> +};
> +
> &uart5 {
> status = "okay";
> };
> diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
> index 1d2fc1e1dc29..aab1889f702f 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
> @@ -31,6 +31,22 @@
> };
> };
>
> +&fmc {
> + status = "okay";
> + flash@0 {
> + status = "okay";
> + label = "bmc";
> + };
> +};
> +
> +&spi {
> + status = "okay";
> + flash@0 {
> + status = "okay";
> + label = "pnor";
> + };
> +};
> +
> &uart5 {
> status = "okay";
> };
> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
> index 0b4932cc02a8..7ef6442d0ade 100644
> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
> @@ -33,6 +33,35 @@
> #size-cells = <1>;
> ranges;
>
> + fmc: flash-controller@1e620000 {
> + reg = < 0x1e620000 0x94
> + 0x20000000 0x02000000 >;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "aspeed,ast2400-fmc";
> + status = "disabled";
> + interrupts = <19>;
> + flash@0 {
> + reg = < 0 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
> + };
> +
> + spi: flash-controller@1e630000 {
> + reg = < 0x1e630000 0x18
> + 0x30000000 0x02000000 >;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "aspeed,ast2400-spi";
> + status = "disabled";
> + flash@0 {
> + reg = < 0 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
> + };
> +
> vic: interrupt-controller@1e6c0080 {
> compatible = "aspeed,ast2400-vic";
> interrupt-controller;
> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
> index b664fe380936..8970f3cb8e2b 100644
> --- a/arch/arm/boot/dts/aspeed-g5.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
> @@ -24,6 +24,69 @@
> #size-cells = <1>;
> ranges;
>
> + fmc: flash-controller@1e620000 {
> + reg = < 0x1e620000 0xc4
> + 0x20000000 0x10000000 >;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "aspeed,ast2500-fmc";
> + status = "disabled";
> + interrupts = <19>;
> + flash@0 {
> + reg = < 0 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
> + flash@1 {
> + reg = < 1 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
> + flash@2 {
> + reg = < 2 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
> + };
> +
> + spi1: flash-controller@1e630000 {
> + reg = < 0x1e630000 0xc4
> + 0x30000000 0x08000000 >;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "aspeed,ast2500-spi";
> + status = "disabled";
> + flash@0 {
> + reg = < 0 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
> + flash@1 {
> + reg = < 1 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
> + };
> +
> + spi2: flash-controller@1e631000 {
> + reg = < 0x1e631000 0xc4
> + 0x38000000 0x08000000 >;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "aspeed,ast2500-spi";
> + status = "disabled";
> + flash@0 {
> + reg = < 0 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
> + flash@1 {
> + reg = < 1 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
> + };
> +
> vic: interrupt-controller@1e6c0080 {
> compatible = "aspeed,ast2400-vic";
> interrupt-controller;
> --
> 2.7.4
>
--
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next prev parent reply other threads:[~2017-03-05 23:13 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-01 14:26 [PATCH 0/2] aspeed: add bindings and defconfig for SPI controllers Cédric Le Goater
2017-03-01 14:26 ` [PATCH 1/2] ARM: dts: aspeed: add SPI controller bindings Cédric Le Goater
[not found] ` <1488378403-24640-2-git-send-email-clg-Bxea+6Xhats@public.gmane.org>
2017-03-05 23:13 ` Joel Stanley [this message]
2017-03-06 7:35 ` Cédric Le Goater
2017-03-01 14:26 ` [PATCH 2/2] ARM: aspeed: Add CONFIG_SPI_ASPEED_SMC Cédric Le Goater
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