From: Joel Stanley <joel@jms.id.au>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Andrew Jeffery <andrew@aj.id.au>,
devicetree <devicetree@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
linux-aspeed@lists.ozlabs.org
Subject: Re: [PATCH v2 2/4] dt-bindings: misc: Aspeed coprocessor interrupt controller
Date: Tue, 19 Jun 2018 16:26:25 +0930 [thread overview]
Message-ID: <CACPK8XfCZA7m++KeJ1GyPAbBXPmyhebEkvb+R41Xy1iuGvkbLw@mail.gmail.com> (raw)
In-Reply-To: <20180618045902.11453-3-benh@kernel.crashing.org>
On 18 June 2018 at 14:29, Benjamin Herrenschmidt
<benh@kernel.crashing.org> wrote:
> Add the device-tree binding definition for the AST2400
> and AST2500 coprocessor interrupt controller
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
> .../devicetree/bindings/misc/aspeed,cvic.txt | 35 +++++++++++++++++++
> 1 file changed, 35 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/misc/aspeed,cvic.txt
>
> diff --git a/Documentation/devicetree/bindings/misc/aspeed,cvic.txt b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt
> new file mode 100644
> index 000000000000..2562e2991e4d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt
Is there a reason you didn't put this in bindings/interrupt-controller?
Aside from that this looks good.
> @@ -0,0 +1,35 @@
> +* Aspeed AST2400 and AST2500 coprocessor interrupt controller
> +
> +This file describes the bindings for the interrupt controller present
> +in the AST2400 and AST2500 BMC SoCs which provides interrupt to the
> +ColdFire coprocessor.
> +
> +It is not a normal interrupt controller and it would be rather
> +inconvenient to create an interrupt tree for it as it somewhat shares
> +some of the same sources as the main ARM interrupt controller but with
> +different numbers.
> +
> +The AST2500 supports a SW generated interrupt
> +
> +Required properties:
> +- reg: address and length of the register for the device.
> +- compatible: "aspeed,cvic" and one of:
> + "aspeed,ast2400-cvic"
> + or
> + "aspeed,ast2500-cvic"
> +
> +- valid-sources: One cell, bitmap of supported sources for the implementation
> +
> +Optional properties;
> +- copro-sw-interrupts: List of interrupt numbers that can be used as
> + SW interrupts from the ARM to the coprocessor.
> + (AST2500 only)
> +
> +Example:
> +
> + cvic: copro-interrupt-controller@1e6c2000 {
> + compatible = "aspeed,ast2500-cvic";
> + valid-sources = <0xffffffff>;
> + copro-sw-interrupts = <1>;
> + reg = <0x1e6c2000 0x80>;
> + };
> --
> 2.17.1
>
next prev parent reply other threads:[~2018-06-19 6:56 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-18 4:58 [PATCH v2 0/4] arm: dts: Aspeed SoC device-tree update Benjamin Herrenschmidt
2018-06-18 4:58 ` [PATCH v2 1/4] arm: dts: Fix error in Aspeed OpenPower Romulus device-tree Benjamin Herrenschmidt
2018-06-18 5:16 ` Benjamin Herrenschmidt
2018-06-18 4:59 ` [PATCH v2 2/4] dt-bindings: misc: Aspeed coprocessor interrupt controller Benjamin Herrenschmidt
2018-06-19 6:56 ` Joel Stanley [this message]
2018-06-19 6:58 ` Benjamin Herrenschmidt
2018-06-20 19:49 ` Rob Herring
2018-06-20 23:05 ` Benjamin Herrenschmidt
2018-06-18 4:59 ` [PATCH v2 3/4] arm: dts: Update AST2500 device-tree Benjamin Herrenschmidt
2018-06-18 4:59 ` [PATCH v2 4/4] arm: dts: Update AST2400 device-tree Benjamin Herrenschmidt
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