* [PATCH 01/17] dt-bindings: vendor-prefixes: Add PLX Technology [not found] ` <1457005210-18485-1-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> @ 2016-03-03 11:39 ` Neil Armstrong 2016-03-03 15:02 ` Philipp Zabel 2016-03-03 11:40 ` [PATCH 14/17] arm: boot: dts: Add PLX Technology OX810SE dtsi Neil Armstrong 1 sibling, 1 reply; 49+ messages in thread From: Neil Armstrong @ 2016-03-03 11:39 UTC (permalink / raw) To: linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA Cc: Neil Armstrong Add PLX Technology vendor prefix. Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 72e2c5a..03970fb 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -178,6 +178,7 @@ picochip Picochip Ltd plathome Plat'Home Co., Ltd. plda PLDA pixcir PIXCIR MICROELECTRONICS Co., Ltd +plxtech PLX Technology, Inc. pulsedlight PulsedLight, Inc powervr PowerVR (deprecated, use img) qca Qualcomm Atheros, Inc. -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [PATCH 01/17] dt-bindings: vendor-prefixes: Add PLX Technology 2016-03-03 11:39 ` [PATCH 01/17] dt-bindings: vendor-prefixes: Add PLX Technology Neil Armstrong @ 2016-03-03 15:02 ` Philipp Zabel 2016-03-05 4:29 ` Rob Herring 0 siblings, 1 reply; 49+ messages in thread From: Philipp Zabel @ 2016-03-03 15:02 UTC (permalink / raw) To: Neil Armstrong; +Cc: linux-kernel, linux-arm-kernel, devicetree Am Donnerstag, den 03.03.2016, 12:39 +0100 schrieb Neil Armstrong: > Add PLX Technology vendor prefix. > > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt > index 72e2c5a..03970fb 100644 > --- a/Documentation/devicetree/bindings/vendor-prefixes.txt > +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt > @@ -178,6 +178,7 @@ picochip Picochip Ltd > plathome Plat'Home Co., Ltd. > plda PLDA > pixcir PIXCIR MICROELECTRONICS Co., Ltd > +plxtech PLX Technology, Inc. The PLX Technology NASDAQ symbol used to be PLXT. Personally, I prefer the more verbose name, just pointing out that "plxt," might also be an option. regards Philipp ^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 01/17] dt-bindings: vendor-prefixes: Add PLX Technology 2016-03-03 15:02 ` Philipp Zabel @ 2016-03-05 4:29 ` Rob Herring 2016-03-07 9:55 ` Philipp Zabel 0 siblings, 1 reply; 49+ messages in thread From: Rob Herring @ 2016-03-05 4:29 UTC (permalink / raw) To: Philipp Zabel, Neil Armstrong; +Cc: linux-kernel, linux-arm-kernel, devicetree On Thu, Mar 03, 2016 at 04:02:15PM +0100, Philipp Zabel wrote: > Am Donnerstag, den 03.03.2016, 12:39 +0100 schrieb Neil Armstrong: > > Add PLX Technology vendor prefix. > > > > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > > --- > > Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt > > index 72e2c5a..03970fb 100644 > > --- a/Documentation/devicetree/bindings/vendor-prefixes.txt > > +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt > > @@ -178,6 +178,7 @@ picochip Picochip Ltd > > plathome Plat'Home Co., Ltd. > > plda PLDA > > pixcir PIXCIR MICROELECTRONICS Co., Ltd > > +plxtech PLX Technology, Inc. > > The PLX Technology NASDAQ symbol used to be PLXT. And is no longer listed? If not, then plxtech is fine. Otherwise, use plxt. Can you fix the alphabetizing while you are at it. Rob ^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 01/17] dt-bindings: vendor-prefixes: Add PLX Technology 2016-03-05 4:29 ` Rob Herring @ 2016-03-07 9:55 ` Philipp Zabel 0 siblings, 0 replies; 49+ messages in thread From: Philipp Zabel @ 2016-03-07 9:55 UTC (permalink / raw) To: Rob Herring; +Cc: Neil Armstrong, linux-kernel, linux-arm-kernel, devicetree Am Freitag, den 04.03.2016, 22:29 -0600 schrieb Rob Herring: > On Thu, Mar 03, 2016 at 04:02:15PM +0100, Philipp Zabel wrote: > > Am Donnerstag, den 03.03.2016, 12:39 +0100 schrieb Neil Armstrong: > > > Add PLX Technology vendor prefix. > > > > > > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > > > --- > > > Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + > > > 1 file changed, 1 insertion(+) > > > > > > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt > > > index 72e2c5a..03970fb 100644 > > > --- a/Documentation/devicetree/bindings/vendor-prefixes.txt > > > +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt > > > @@ -178,6 +178,7 @@ picochip Picochip Ltd > > > plathome Plat'Home Co., Ltd. > > > plda PLDA > > > pixcir PIXCIR MICROELECTRONICS Co., Ltd > > > +plxtech PLX Technology, Inc. > > > > The PLX Technology NASDAQ symbol used to be PLXT. > > And is no longer listed? If not, then plxtech is fine. Otherwise, use > plxt. PLXT was listed until August 2014, when Avago (now Broadcom Limited) acquired PLX Technology. regards Philipp ^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 14/17] arm: boot: dts: Add PLX Technology OX810SE dtsi [not found] ` <1457005210-18485-1-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> 2016-03-03 11:39 ` [PATCH 01/17] dt-bindings: vendor-prefixes: Add PLX Technology Neil Armstrong @ 2016-03-03 11:40 ` Neil Armstrong 2016-03-03 12:15 ` Arnd Bergmann 1 sibling, 1 reply; 49+ messages in thread From: Neil Armstrong @ 2016-03-03 11:40 UTC (permalink / raw) To: linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-lFZ/pmaqli7XmaaqVzeoHQ Cc: Neil Armstrong Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> --- arch/arm/boot/dts/ox810se.dtsi | 279 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 279 insertions(+) create mode 100644 arch/arm/boot/dts/ox810se.dtsi diff --git a/arch/arm/boot/dts/ox810se.dtsi b/arch/arm/boot/dts/ox810se.dtsi new file mode 100644 index 0000000..a86d7f0 --- /dev/null +++ b/arch/arm/boot/dts/ox810se.dtsi @@ -0,0 +1,279 @@ +/* + * ox810se.dtsi - Device tree file for PLX Technology OX810SE SoC + * + * Copyright (C) 2016 Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> + * + * Licensed under GPLv2 or later + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "plxtech,ox810se"; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + clocks = <&armclk>; + }; + }; + + memory { + /* Max 256MB @ 0x48000000 */ + reg = <0x48000000 0x10000000>; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + gpio0 = &gpio0; + gpio1 = &gpio1; + }; + + clocks { + osc: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + gmacclk: gmacclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + rpsclk: rspclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&osc>; + }; + + pll400: pll400 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <733333333>; + }; + + sysclk: sysclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clocks = <&pll400>; + }; + + armclk: armclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clocks = <&pll400>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&intc>; + + apb-bridge@44000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x44000000 0x1000000>; + + pinctrl: pinctrl { + compatible = "plxtech,nas782x-pinctrl", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Regmap for sys registers */ + plxtech,sys-ctrl = <&sys>; + + /* Default, all-open mux-map */ + plxtech,mux-mask = < + 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF + >; + + gpio0: gpio@000000 { + compatible = "plxtech,nas782x-gpio"; + reg = <0x000000 0x100000>; + interrupts = <21>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-lines = <32>; + }; + + gpio1: gpio@100000 { + compatible = "plxtech,nas782x-gpio"; + reg = <0x100000 0x100000>; + interrupts = <22>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-lines = <3>; + }; + + uart0 { + pinctrl_uart0: uart0 { + plxtech,pins = <0 31 3 0 + 0 32 3 0>; + }; + pinctrl_uart0_modem: uart0_modem { + plxtech,pins = <0 27 3 0 + 0 28 3 0 + 0 29 3 0 + 0 30 3 0 + 0 33 3 0 + 0 34 3 0>; + }; + }; + + uart1 { + pinctrl_uart1: uart1 { + plxtech,pins = <0 20 3 0 + 0 22 3 0>; + }; + pinctrl_uart1_modem: uart1_modem { + plxtech,pins = <0 8 3 0 + 0 9 3 0 + 0 23 3 0 + 0 24 3 0 + 0 25 3 0 + 0 26 3 0>; + }; + }; + + uart2 { + pinctrl_uart2: uart2 { + plxtech,pins = <0 6 3 0 + 0 7 3 0>; + }; + pinctrl_uart2_modem: uart2_modem { + plxtech,pins = <0 0 3 0 + 0 1 3 0 + 0 2 3 0 + 0 3 3 0 + 0 4 3 0 + 0 5 3 0>; + }; + }; + }; + + uart0: uart@200000 { + compatible = "ns16550a"; + reg = <0x200000 0x100000>; + clocks = <&sysclk>; + interrupts = <23>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 17>; + }; + + uart1: uart@300000 { + compatible = "ns16550a"; + reg = <0x300000 0x100000>; + clocks = <&sysclk>; + interrupts = <24>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 18>; + }; + + uart2: uart@900000 { + compatible = "ns16550a"; + reg = <0x900000 0x100000>; + clocks = <&sysclk>; + interrupts = <29>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 22>; + }; + + uart3: uart@a00000 { + compatible = "ns16550a"; + reg = <0xa00000 0x100000>; + clocks = <&sysclk>; + interrupts = <30>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 23>; + }; + }; + + apb-bridge@45000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x45000000 0x1000000>; + + sys: sys-ctrl@000000 { + compatible = "plxtech,ox810se-sys-ctrl", "syscon", "simple-mfd"; + reg = <0x000000 0x100000>; + + reset: reset-controller { + compatible = "plxtech,nas782x-reset"; + #reset-cells = <1>; + }; + + stdclk: stdclk { + compatible = "plxtech,ox810se-stdclk", "plxtech,nas782x-stdclk"; + #clock-cells = <1>; + }; + }; + + rps@300000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x300000 0x100000>; + + intc: interrupt-controller@0 { + compatible = "plxtech,nas782x-rps"; + interrupt-controller; + reg = <0 0x200>; + #interrupt-cells = <1>; + }; + + timer0: timer@200 { + compatible = "plxtech,nas782x-rps-timer"; + reg = <0x200 0x40>; + clocks = <&rpsclk>; + interrupts = <4 5>; + }; + }; + }; + }; +}; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [PATCH 14/17] arm: boot: dts: Add PLX Technology OX810SE dtsi 2016-03-03 11:40 ` [PATCH 14/17] arm: boot: dts: Add PLX Technology OX810SE dtsi Neil Armstrong @ 2016-03-03 12:15 ` Arnd Bergmann 2016-03-03 13:39 ` Neil Armstrong 0 siblings, 1 reply; 49+ messages in thread From: Arnd Bergmann @ 2016-03-03 12:15 UTC (permalink / raw) To: linux-arm-kernel; +Cc: Neil Armstrong, linux-kernel, devicetree, linux On Thursday 03 March 2016 12:40:07 Neil Armstrong wrote: > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + serial2 = &uart2; > + serial3 = &uart3; > + gpio0 = &gpio0; > + gpio1 = &gpio1; > + }; > Please put the aliases in the per-board file and list only the devices that are actually connected (in case of uart) > + uart0: uart@200000 { Make this serial@200000, to follow the standard naming convention > + > + reset: reset-controller { > + compatible = "plxtech,nas782x-reset"; > + #reset-cells = <1>; > + }; > + > + stdclk: stdclk { > + compatible = "plxtech,ox810se-stdclk", "plxtech,nas782x-stdclk"; > + #clock-cells = <1>; > + }; > + }; Please change the compatible strings to have no 'x' wildcards in them, but instead use a specific model. Regarding the vendor prefixes, my understanding is that "ox810se" was the name of the chip from Oxford Semiconductor, while nas7820 is a product name from PLX. I think it would be logical to use "oxford" as the vendor prefix for anything with a ox810se or ox820 ID in it rather than plxtech. Note that both of them are now historic, as PLX itself got bought by Avago and they seem to be discontinuing both the PLX and Oxfor brand names. Arnd ^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 14/17] arm: boot: dts: Add PLX Technology OX810SE dtsi 2016-03-03 12:15 ` Arnd Bergmann @ 2016-03-03 13:39 ` Neil Armstrong 0 siblings, 0 replies; 49+ messages in thread From: Neil Armstrong @ 2016-03-03 13:39 UTC (permalink / raw) To: Arnd Bergmann, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-lFZ/pmaqli7XmaaqVzeoHQ On 03/03/2016 01:15 PM, Arnd Bergmann wrote: > On Thursday 03 March 2016 12:40:07 Neil Armstrong wrote: >> + >> + aliases { >> + serial0 = &uart0; >> + serial1 = &uart1; >> + serial2 = &uart2; >> + serial3 = &uart3; >> + gpio0 = &gpio0; >> + gpio1 = &gpio1; >> + }; >> > Please put the aliases in the per-board file and list only the > devices that are actually connected (in case of uart) Done. > >> + uart0: uart@200000 { > > Make this serial@200000, to follow the standard naming convention Done. > >> + >> + reset: reset-controller { >> + compatible = "plxtech,nas782x-reset"; >> + #reset-cells = <1>; >> + }; >> + >> + stdclk: stdclk { >> + compatible = "plxtech,ox810se-stdclk", "plxtech,nas782x-stdclk"; >> + #clock-cells = <1>; >> + }; >> + }; > > Please change the compatible strings to have no 'x' wildcards in them, but > instead use a specific model. Ok, I switched to only oxsemi,ox810se-* strings. > > Regarding the vendor prefixes, my understanding is that "ox810se" was the name > of the chip from Oxford Semiconductor, while nas7820 is a product name from > PLX. I think it would be logical to use "oxford" as the vendor prefix > for anything with a ox810se or ox820 ID in it rather than plxtech. Ok, I switched to oxsemi but keeped plxtech and added oxsemi in the vendor prefixes. > > Note that both of them are now historic, as PLX itself got bought by > Avago and they seem to be discontinuing both the PLX and Oxfor brand > names. Yes, it's kind of a mess. The ox820 has been rebranded to plx7821, but not the ox810... > > Arnd > Thanks, Neil -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 03/17] dt-bindings: Add PLX Technology RPS IRQ Controller bindings [not found] <1457005210-18485-1-git-send-email-narmstrong@baylibre.com> [not found] ` <1457005210-18485-1-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> @ 2016-03-03 11:39 ` Neil Armstrong 2016-03-03 14:53 ` Andrew Lunn 2016-03-03 11:39 ` [PATCH 05/17] dt-bindings: Add PLX Technology RPS Timer bindings Neil Armstrong ` (7 subsequent siblings) 9 siblings, 1 reply; 49+ messages in thread From: Neil Armstrong @ 2016-03-03 11:39 UTC (permalink / raw) To: linux-kernel, linux-arm-kernel, devicetree; +Cc: Neil Armstrong Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- .../bindings/interrupt-controller/plxtech,rps-irq.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/plxtech,rps-irq.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/plxtech,rps-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/plxtech,rps-irq.txt new file mode 100644 index 0000000..db117a0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/plxtech,rps-irq.txt @@ -0,0 +1,17 @@ +PLX Technology OXNAS SoCs Family RPS Interrupt Controller +========================================================= + +Required properties: +- compatible: Should be "plxtech,nas782x-rps" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Should be 1 + +example: + +intc: interrupt-controller@0 { + compatible = "plxtech,nas782x-rps"; + interrupt-controller; + reg = <0 0x200>; + #interrupt-cells = <1>; +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [PATCH 03/17] dt-bindings: Add PLX Technology RPS IRQ Controller bindings 2016-03-03 11:39 ` [PATCH 03/17] dt-bindings: Add PLX Technology RPS IRQ Controller bindings Neil Armstrong @ 2016-03-03 14:53 ` Andrew Lunn 2016-03-03 14:57 ` Neil Armstrong 0 siblings, 1 reply; 49+ messages in thread From: Andrew Lunn @ 2016-03-03 14:53 UTC (permalink / raw) To: Neil Armstrong; +Cc: linux-kernel, linux-arm-kernel, devicetree On Thu, Mar 03, 2016 at 12:39:56PM +0100, Neil Armstrong wrote: > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > .../bindings/interrupt-controller/plxtech,rps-irq.txt | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/plxtech,rps-irq.txt > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/plxtech,rps-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/plxtech,rps-irq.txt > new file mode 100644 > index 0000000..db117a0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/plxtech,rps-irq.txt ... > +- compatible: Should be "plxtech,nas782x-rps" Hi Neil It would be nice to be consistent with the naming. Maybe also the filename of the driver itself should be changed. You had an interesting sorting problem in the Makefile, which a consistent name would help with. Andrew ^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 03/17] dt-bindings: Add PLX Technology RPS IRQ Controller bindings 2016-03-03 14:53 ` Andrew Lunn @ 2016-03-03 14:57 ` Neil Armstrong [not found] ` <56D850C6.1010404-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> 0 siblings, 1 reply; 49+ messages in thread From: Neil Armstrong @ 2016-03-03 14:57 UTC (permalink / raw) To: Andrew Lunn; +Cc: linux-kernel, linux-arm-kernel, devicetree Hi Andrew, On 03/03/2016 03:53 PM, Andrew Lunn wrote: > >> +- compatible: Should be "plxtech,nas782x-rps" > > Hi Neil > > It would be nice to be consistent with the naming. The compatible is now oxsemi,os810se-rps-irq which is consistent with the timer. > > Maybe also the filename of the driver itself should be changed. You > had an interesting sorting problem in the Makefile, which a consistent > name would help with. Yes, I will add -irq to the driver name and _IRQ to the config name. > > Andrew > Thanks, Neil ^ permalink raw reply [flat|nested] 49+ messages in thread
[parent not found: <56D850C6.1010404-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>]
* Re: [PATCH 03/17] dt-bindings: Add PLX Technology RPS IRQ Controller bindings [not found] ` <56D850C6.1010404-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> @ 2016-03-03 15:06 ` Andrew Lunn 0 siblings, 0 replies; 49+ messages in thread From: Andrew Lunn @ 2016-03-03 15:06 UTC (permalink / raw) To: Neil Armstrong Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On Thu, Mar 03, 2016 at 03:57:10PM +0100, Neil Armstrong wrote: > Hi Andrew, > > On 03/03/2016 03:53 PM, Andrew Lunn wrote: > > > >> +- compatible: Should be "plxtech,nas782x-rps" > > > > Hi Neil > > > > It would be nice to be consistent with the naming. > The compatible is now oxsemi,os810se-rps-irq which is consistent with the timer. Ah, i had not read that far down the thread yet. Thanks Andrew -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 05/17] dt-bindings: Add PLX Technology RPS Timer bindings [not found] <1457005210-18485-1-git-send-email-narmstrong@baylibre.com> [not found] ` <1457005210-18485-1-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> 2016-03-03 11:39 ` [PATCH 03/17] dt-bindings: Add PLX Technology RPS IRQ Controller bindings Neil Armstrong @ 2016-03-03 11:39 ` Neil Armstrong 2016-03-03 11:40 ` [PATCH 07/17] dt-bindings: Add PLX Technology Reset Controller bindings Neil Armstrong ` (6 subsequent siblings) 9 siblings, 0 replies; 49+ messages in thread From: Neil Armstrong @ 2016-03-03 11:39 UTC (permalink / raw) To: linux-kernel, linux-arm-kernel, devicetree; +Cc: Neil Armstrong Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- .../devicetree/bindings/timer/plxtech,rps-timer.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/plxtech,rps-timer.txt diff --git a/Documentation/devicetree/bindings/timer/plxtech,rps-timer.txt b/Documentation/devicetree/bindings/timer/plxtech,rps-timer.txt new file mode 100644 index 0000000..bc7cb33 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/plxtech,rps-timer.txt @@ -0,0 +1,17 @@ +PLX Technology OXNAS SoCs Family RPS Timer +========================================== + +Required properties: +- compatible: Should be "plxtech,nas782x-rps-timer" +- reg : Specifies base physical address and size of the registers. +- interrupts : The interrupt of the first timer +- clocks : The phandle of the timer clock source + +example: + +timer0: timer@200 { + compatible = "plxtech,nas782x-rps-timer"; + reg = <0x200 0x40>; + clocks = <&rpsclk>; + interrupts = <4 5>; +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 07/17] dt-bindings: Add PLX Technology Reset Controller bindings [not found] <1457005210-18485-1-git-send-email-narmstrong@baylibre.com> ` (2 preceding siblings ...) 2016-03-03 11:39 ` [PATCH 05/17] dt-bindings: Add PLX Technology RPS Timer bindings Neil Armstrong @ 2016-03-03 11:40 ` Neil Armstrong 2016-03-03 14:21 ` Philipp Zabel 2016-03-03 11:40 ` [PATCH 09/17] dt-bindings: Add PLX Technology OXNAS Standard Clocks bindings Neil Armstrong ` (5 subsequent siblings) 9 siblings, 1 reply; 49+ messages in thread From: Neil Armstrong @ 2016-03-03 11:40 UTC (permalink / raw) To: linux-kernel, linux-arm-kernel, devicetree; +Cc: Neil Armstrong Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- .../devicetree/bindings/reset/plxtech,reset.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/plxtech,reset.txt diff --git a/Documentation/devicetree/bindings/reset/plxtech,reset.txt b/Documentation/devicetree/bindings/reset/plxtech,reset.txt new file mode 100644 index 0000000..e99648d --- /dev/null +++ b/Documentation/devicetree/bindings/reset/plxtech,reset.txt @@ -0,0 +1,25 @@ +PLX Technology OXNAS SoC Family RESET Controller +================================================ + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be "plxtech,nas782x-reset" +- #reset-cells: 1, see below + +Parent node should have the following properties : +- compatible: Should be "plxtech,ox810se-sys-ctrl", "syscon", "simple-mfd" + +example: + +sys: sys-ctrl@000000 { + compatible = "plxtech,ox810se-sys-ctrl", "syscon", "simple-mfd"; + reg = <0x000000 0x100000>; + + reset: reset-controller { + compatible = "plxtech,nas782x-reset"; + #reset-cells = <1>; + + }; +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [PATCH 07/17] dt-bindings: Add PLX Technology Reset Controller bindings 2016-03-03 11:40 ` [PATCH 07/17] dt-bindings: Add PLX Technology Reset Controller bindings Neil Armstrong @ 2016-03-03 14:21 ` Philipp Zabel [not found] ` <1457014907.3425.56.camel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> 0 siblings, 1 reply; 49+ messages in thread From: Philipp Zabel @ 2016-03-03 14:21 UTC (permalink / raw) To: Neil Armstrong; +Cc: linux-kernel, linux-arm-kernel, devicetree Am Donnerstag, den 03.03.2016, 12:40 +0100 schrieb Neil Armstrong: > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > .../devicetree/bindings/reset/plxtech,reset.txt | 25 ++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > create mode 100644 Documentation/devicetree/bindings/reset/plxtech,reset.txt > > diff --git a/Documentation/devicetree/bindings/reset/plxtech,reset.txt b/Documentation/devicetree/bindings/reset/plxtech,reset.txt > new file mode 100644 > index 0000000..e99648d > --- /dev/null > +++ b/Documentation/devicetree/bindings/reset/plxtech,reset.txt > @@ -0,0 +1,25 @@ > +PLX Technology OXNAS SoC Family RESET Controller > +================================================ > + > +Please also refer to reset.txt in this directory for common reset > +controller binding usage. > + > +Required properties: > +- compatible: Should be "plxtech,nas782x-reset" > +- #reset-cells: 1, see below > + > +Parent node should have the following properties : > +- compatible: Should be "plxtech,ox810se-sys-ctrl", "syscon", "simple-mfd" > + > +example: > + > +sys: sys-ctrl@000000 { > + compatible = "plxtech,ox810se-sys-ctrl", "syscon", "simple-mfd"; > + reg = <0x000000 0x100000>; > + > + reset: reset-controller { > + compatible = "plxtech,nas782x-reset"; > + #reset-cells = <1>; > + > + }; > +}; Is there a list of the reset bits in this register? regards Philipp ^ permalink raw reply [flat|nested] 49+ messages in thread
[parent not found: <1457014907.3425.56.camel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>]
* Re: [PATCH 07/17] dt-bindings: Add PLX Technology Reset Controller bindings [not found] ` <1457014907.3425.56.camel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> @ 2016-03-03 14:24 ` Neil Armstrong 2016-03-03 14:31 ` Philipp Zabel 0 siblings, 1 reply; 49+ messages in thread From: Neil Armstrong @ 2016-03-03 14:24 UTC (permalink / raw) To: Philipp Zabel Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA On 03/03/2016 03:21 PM, Philipp Zabel wrote: > Am Donnerstag, den 03.03.2016, 12:40 +0100 schrieb Neil Armstrong: >> Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> > > Is there a list of the reset bits in this register? > > regards > Philipp > Yes, should I add it to the bindings ? Neil -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 07/17] dt-bindings: Add PLX Technology Reset Controller bindings 2016-03-03 14:24 ` Neil Armstrong @ 2016-03-03 14:31 ` Philipp Zabel 0 siblings, 0 replies; 49+ messages in thread From: Philipp Zabel @ 2016-03-03 14:31 UTC (permalink / raw) To: Neil Armstrong; +Cc: linux-kernel, linux-arm-kernel, devicetree Am Donnerstag, den 03.03.2016, 15:24 +0100 schrieb Neil Armstrong: > On 03/03/2016 03:21 PM, Philipp Zabel wrote: > > Am Donnerstag, den 03.03.2016, 12:40 +0100 schrieb Neil Armstrong: > >> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > > > > Is there a list of the reset bits in this register? > > > > regards > > Philipp > > > > Yes, should I add it to the bindings ? Yes, please. Either that or add a header file with #defines to include/dt-bindings/reset and use it in the dtsi. regards Philipp ^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 09/17] dt-bindings: Add PLX Technology OXNAS Standard Clocks bindings [not found] <1457005210-18485-1-git-send-email-narmstrong@baylibre.com> ` (3 preceding siblings ...) 2016-03-03 11:40 ` [PATCH 07/17] dt-bindings: Add PLX Technology Reset Controller bindings Neil Armstrong @ 2016-03-03 11:40 ` Neil Armstrong 2016-03-03 11:40 ` [PATCH 11/17] dt-bindings: Add PLX Technology OXNAS pinctrl and gpio bindings Neil Armstrong ` (4 subsequent siblings) 9 siblings, 0 replies; 49+ messages in thread From: Neil Armstrong @ 2016-03-03 11:40 UTC (permalink / raw) To: linux-kernel, linux-arm-kernel, devicetree; +Cc: Neil Armstrong Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- .../devicetree/bindings/clock/plxtech,stdclk.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/plxtech,stdclk.txt diff --git a/Documentation/devicetree/bindings/clock/plxtech,stdclk.txt b/Documentation/devicetree/bindings/clock/plxtech,stdclk.txt new file mode 100644 index 0000000..46465c6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/plxtech,stdclk.txt @@ -0,0 +1,24 @@ +PLX Technology OXNAS SoC Family Standard Clocks +================================================ + +Please also refer to clock-bindings.txt in this directory for common clock +bindings usage. + +Required properties: +- compatible: Should be "plxtech,ox810se-stdclk" or "plxtech,nas782x-stdclk" +- #clock-cells: 1, see below + +Parent node should have the following properties : +- compatible: Should be "plxtech,ox810se-sys-ctrl", "syscon", "simple-mfd" + +example: + +sys: sys-ctrl@000000 { + compatible = "plxtech,ox810se-sys-ctrl", "syscon", "simple-mfd"; + reg = <0x000000 0x100000>; + + stdclk: stdclk { + compatible = "plxtech,ox810se-stdclk", "plxtech,nas782x-stdclk"; + #reset-cells = <1>; + }; +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 11/17] dt-bindings: Add PLX Technology OXNAS pinctrl and gpio bindings [not found] <1457005210-18485-1-git-send-email-narmstrong@baylibre.com> ` (4 preceding siblings ...) 2016-03-03 11:40 ` [PATCH 09/17] dt-bindings: Add PLX Technology OXNAS Standard Clocks bindings Neil Armstrong @ 2016-03-03 11:40 ` Neil Armstrong [not found] ` <1457005210-18485-12-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> 2016-03-03 11:40 ` [PATCH 15/17] dt-bindings: Add OXNAS bindings Neil Armstrong ` (3 subsequent siblings) 9 siblings, 1 reply; 49+ messages in thread From: Neil Armstrong @ 2016-03-03 11:40 UTC (permalink / raw) To: linux-kernel, linux-arm-kernel, devicetree; +Cc: Neil Armstrong Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- .../devicetree/bindings/gpio/gpio_oxnas.txt | 27 ++++++ .../bindings/pinctrl/plxtech,pinctrl.txt | 100 +++++++++++++++++++++ 2 files changed, 127 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio_oxnas.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt diff --git a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt new file mode 100644 index 0000000..0ef6c55 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt @@ -0,0 +1,27 @@ +PLX Technology OXNAS SoC GPIO Controller +========================================== + +Required properties: +- compatible: "plxtech,nas782x-gpio". +- reg: Should contain GPIO controller registers location and length +- interrupts: Should be the port interrupt shared by all the pins. +- #gpio-cells: Should be two. The first cell is the pin number and + the second cell is used to specify optional parameters (currently + unused). +- gpio-controller: Marks the device node as a GPIO controller. + +optional properties: +- #gpio-lines: Number of gpio if absent 32. + + +Example: + gpio0: gpio@000000 { + compatible = "plxtech,nas782x-gpio"; + reg = <0x000000 0x100000>; + interrupts = <21>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-lines = <32>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt new file mode 100644 index 0000000..30f013f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt @@ -0,0 +1,100 @@ +PLX Technology OXNAS SoC Pinmux Controller +========================================== + +The OXNAS Pinmux Controller, enables the IC to share one PAD to several +functional blocks. The sharing is done by multiplexing the PAD input/output +signals. For each PAD there are up to 8 muxing options (called periph modes). +Since different modules require different PAD settings +(like pull up, keeper, etc) the contoller controls also the PAD settings +parameters. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +OXNAS pin configuration node is a node of a group of pins which can be +used for a specific device or function. This node represents both mux and config +of the pins in that group. The 'pins' selects the function mode(also named pin +mode) this pin can work on and the 'config' configures various pad settings +such as pull-up, multi drive, etc. + +Required properties for iomux controller: +- compatible: "plxtech,nas782x-pinctrl" or "plxtech,ox810se-pinctrl" +- plxtech,mux-mask: array of mask (periph per bank) to describe if a pin can be + configured in this periph mode. All the periph and bank need to be describe. +- plxtech,sys-ctrl: a phandle to the system controller syscon node + +How to create such array: + +Each column will represent the possible peripheral of the pinctrl +Each line will represent a pio bank + +For example : +Peripheral: 2 ( A and B) +Bank: 2 (A, B and C) +=> + + /* A B */ + 0xffffffff 0xffc00c3b /* pioA */ + 0xffffffff 0x7fff3ccf /* pioB */ + +For each peripheral/bank we will descibe in a u32 if a pin can be +configured in it by putting 1 to the pin bit (1 << pin) + +Required properties for pin configuration node: +- plxtech,pins: 4 integers array, represents a group of pins mux and config + setting. The format is plxtech,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>. + The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B... + PIN_BANK 0 is pioA, PIN_BANK 1 is pioB... + +Bits used for CONFIG: + - None Yet + +Examples: + +pinctrl: pinctrl { + compatible = "plxtech,nas782x-pinctrl", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Regmap for sys registers */ + plxtech,sys-ctrl = <&sys>; + + /* Default, all-open mux-map */ + plxtech,mux-mask = < + 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF + >; + + uart0 { + pinctrl_uart0: uart0 { + plxtech,pins = <0 31 3 0 + 0 32 3 0>; + }; + pinctrl_uart0_modem: uart0_modem { + plxtech,pins = <0 27 3 0 + 0 28 3 0 + 0 29 3 0 + 0 30 3 0 + 0 33 3 0 + 0 34 3 0>; + }; + }; +}; + +uart0: uart@200000 { + compatible = "ns16550a"; + reg = <0x200000 0x100000>; + clocks = <&sysclk>; + interrupts = <23>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 17>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 49+ messages in thread
[parent not found: <1457005210-18485-12-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>]
* Re: [PATCH 11/17] dt-bindings: Add PLX Technology OXNAS pinctrl and gpio bindings [not found] ` <1457005210-18485-12-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> @ 2016-03-15 14:30 ` Linus Walleij 0 siblings, 0 replies; 49+ messages in thread From: Linus Walleij @ 2016-03-15 14:30 UTC (permalink / raw) To: Neil Armstrong Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org On Thu, Mar 3, 2016 at 12:40 PM, Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> wrote: This is a vert terse zero-line commit message. Atleast describe what you are trying to do. > Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> > +optional properties: > +- #gpio-lines: Number of gpio if absent 32. NACK, use ngpio from the gpio.txt document like everyone else. > +Required properties for iomux controller: > +- compatible: "plxtech,nas782x-pinctrl" or "plxtech,ox810se-pinctrl" > +- plxtech,mux-mask: array of mask (periph per bank) to describe if a pin can be > + configured in this periph mode. All the periph and bank need to be describe. Why? Encode this into the driver and select muxmask from the compatible string if it is a hardware limitation. > +Each column will represent the possible peripheral of the pinctrl > +Each line will represent a pio bank > + > +For example : > +Peripheral: 2 ( A and B) > +Bank: 2 (A, B and C) > +=> > + > + /* A B */ > + 0xffffffff 0xffc00c3b /* pioA */ > + 0xffffffff 0x7fff3ccf /* pioB */ > + > +For each peripheral/bank we will descibe in a u32 if a pin can be > +configured in it by putting 1 to the pin bit (1 << pin) That's just completely hopeless to understand for a DT author. Put it into the driver. > +Required properties for pin configuration node: > +- plxtech,pins: 4 integers array, represents a group of pins mux and config > + setting. The format is plxtech,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>. > + The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B... > + PIN_BANK 0 is pioA, PIN_BANK 1 is pioB... NACK, use the standard binding for "pins" from pinctrl-bindings.txt Also make the driver use the existing helpers for this property. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 15/17] dt-bindings: Add OXNAS bindings [not found] <1457005210-18485-1-git-send-email-narmstrong@baylibre.com> ` (5 preceding siblings ...) 2016-03-03 11:40 ` [PATCH 11/17] dt-bindings: Add PLX Technology OXNAS pinctrl and gpio bindings Neil Armstrong @ 2016-03-03 11:40 ` Neil Armstrong 2016-03-03 11:40 ` [PATCH 16/17] dt-bindings: Add Western Digital to vendor prefixes Neil Armstrong ` (2 subsequent siblings) 9 siblings, 0 replies; 49+ messages in thread From: Neil Armstrong @ 2016-03-03 11:40 UTC (permalink / raw) To: linux-kernel, linux-arm-kernel, devicetree; +Cc: Neil Armstrong Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- Documentation/devicetree/bindings/arm/oxnas.txt | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/oxnas.txt diff --git a/Documentation/devicetree/bindings/arm/oxnas.txt b/Documentation/devicetree/bindings/arm/oxnas.txt new file mode 100644 index 0000000..6e17ca4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/oxnas.txt @@ -0,0 +1,9 @@ +PLX Technology OXNAS SoCs Family device tree bindings +------------------------------------------- + +Boards with the OX810SE Soc SoC shall have the following properties: + Required root node property: + compatible: "plxtech,ox810se" + +Board compatible values: + - "wd,mbwe" (OX810SE) -- 1.9.1 ^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 16/17] dt-bindings: Add Western Digital to vendor prefixes [not found] <1457005210-18485-1-git-send-email-narmstrong@baylibre.com> ` (6 preceding siblings ...) 2016-03-03 11:40 ` [PATCH 15/17] dt-bindings: Add OXNAS bindings Neil Armstrong @ 2016-03-03 11:40 ` Neil Armstrong 2016-03-05 4:29 ` Rob Herring 2016-03-03 11:40 ` [PATCH 17/17] arm: boot: dts: Add Western Digital My Book World Edition device tree Neil Armstrong [not found] ` <1457519060-6038-1-git-send-email-narmstrong@baylibre.com> 9 siblings, 1 reply; 49+ messages in thread From: Neil Armstrong @ 2016-03-03 11:40 UTC (permalink / raw) To: linux-kernel, linux-arm-kernel, devicetree; +Cc: Neil Armstrong Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 03970fb..4055608 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -248,6 +248,7 @@ via VIA Technologies, Inc. virtio Virtual I/O Device Specification, developed by the OASIS consortium vivante Vivante Corporation voipac Voipac Technologies s.r.o. +wd Western Digital Corp. wexler Wexler winbond Winbond Electronics corp. wlf Wolfson Microelectronics -- 1.9.1 ^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [PATCH 16/17] dt-bindings: Add Western Digital to vendor prefixes 2016-03-03 11:40 ` [PATCH 16/17] dt-bindings: Add Western Digital to vendor prefixes Neil Armstrong @ 2016-03-05 4:29 ` Rob Herring 0 siblings, 0 replies; 49+ messages in thread From: Rob Herring @ 2016-03-05 4:29 UTC (permalink / raw) To: Neil Armstrong; +Cc: linux-kernel, linux-arm-kernel, devicetree On Thu, Mar 03, 2016 at 12:40:09PM +0100, Neil Armstrong wrote: > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + > 1 file changed, 1 insertion(+) Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 17/17] arm: boot: dts: Add Western Digital My Book World Edition device tree [not found] <1457005210-18485-1-git-send-email-narmstrong@baylibre.com> ` (7 preceding siblings ...) 2016-03-03 11:40 ` [PATCH 16/17] dt-bindings: Add Western Digital to vendor prefixes Neil Armstrong @ 2016-03-03 11:40 ` Neil Armstrong [not found] ` <1457519060-6038-1-git-send-email-narmstrong@baylibre.com> 9 siblings, 0 replies; 49+ messages in thread From: Neil Armstrong @ 2016-03-03 11:40 UTC (permalink / raw) To: linux-kernel, linux-arm-kernel, devicetree, linux; +Cc: Neil Armstrong Add Western Digital My Book World Edition device tree based on PLX Technology OX810SE SoC. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/wd-mbwe.dts | 106 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 108 insertions(+) create mode 100644 arch/arm/boot/dts/wd-mbwe.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a4a6d70..0395674 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -520,6 +520,8 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ orion5x-rd88f5182-nas.dtb dtb-$(CONFIG_ARCH_PRIMA2) += \ prima2-evb.dtb +dtb-$(CONFIG_ARCH_OXNAS) += \ + wd-mbwe.dtb dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8064-cm-qs600.dtb \ qcom-apq8064-ifc6410.dtb \ diff --git a/arch/arm/boot/dts/wd-mbwe.dts b/arch/arm/boot/dts/wd-mbwe.dts new file mode 100644 index 0000000..ad97e2f --- /dev/null +++ b/arch/arm/boot/dts/wd-mbwe.dts @@ -0,0 +1,106 @@ +/* + * wd-mbwe.dtsi - Device tree file for Western Digital My Book World Edition + * + * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> + * + * Licensed under GPLv2 or later + */ + +/dts-v1/; +#include "ox810se.dtsi" + +/ { + model = "Western Digital My Book World Edition"; + + compatible = "wd,mbwe", "plxtech,ox810se"; + + chosen { + bootargs = "console=ttyS1,115200n8 earlyprintk=serial"; + }; + + memory { + /* 128Mbytes DDR */ + reg = <0x48000000 0x8000000>; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + power { + label = "power"; + gpios = <&gpio0 0 1>; + linux,code = <0x198>; + }; + + recovery { + label = "recovery"; + gpios = <&gpio0 4 1>; + linux,code = <0xab>; + }; + }; + + leds { + compatible = "gpio-leds"; + + a0 { + label = "activity0"; + gpios = <&gpio0 25 0>; + default-state = "keep"; + }; + + a1 { + label = "activity1"; + gpios = <&gpio0 26 0>; + default-state = "keep"; + }; + + a2 { + label = "activity2"; + gpios = <&gpio0 5 0>; + default-state = "keep"; + }; + + a3 { + label = "activity3"; + gpios = <&gpio0 6 0>; + default-state = "keep"; + }; + + a4 { + label = "activity4"; + gpios = <&gpio0 7 0>; + default-state = "keep"; + }; + + a5 { + label = "activity5"; + gpios = <&gpio1 2 0>; + default-state = "keep"; + }; + }; + + i2c-gpio { + compatible = "i2c-gpio"; + gpios = <&gpio0 3 0 /* sda */ + &gpio0 2 0 /* scl */ + >; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + + rtc0: rtc@48 { + compatible = "st,m41t00"; + reg = <0x68>; + }; + }; +}; + +&uart1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 49+ messages in thread
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* [PATCH v2 02/18] dt-bindings: timer: sp804: add timer-width property [not found] ` <1457519060-6038-1-git-send-email-narmstrong@baylibre.com> @ 2016-03-09 10:24 ` Neil Armstrong [not found] ` <1457519060-6038-3-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> 2016-03-09 10:24 ` [PATCH v2 04/18] dt-bindings: irq: arm,versatile-fpga: add arm,rps-irq compatible string Neil Armstrong ` (8 subsequent siblings) 9 siblings, 1 reply; 49+ messages in thread From: Neil Armstrong @ 2016-03-09 10:24 UTC (permalink / raw) To: linux-kernel, linux-arm-kernel, daniel.lezcano, tglx, rmk+kernel, sudeep.holla, devicetree Cc: Neil Armstrong Add timer-width optional property to specify a different vendor specific timer counter bit-width. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- Documentation/devicetree/bindings/timer/arm,sp804.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/arm,sp804.txt b/Documentation/devicetree/bindings/timer/arm,sp804.txt index 5cd8eee7..141e143 100644 --- a/Documentation/devicetree/bindings/timer/arm,sp804.txt +++ b/Documentation/devicetree/bindings/timer/arm,sp804.txt @@ -17,6 +17,8 @@ Optional properties: - arm,sp804-has-irq = <#>: In the case of only 1 timer irq line connected, this specifies if the irq connection is for timer 1 or timer 2. A value of 1 or 2 should be used. +- arm,timer-width: Should contain the width in number of bits of the counter, + is considered by default 32 but can be changed for vendor variants. Example: -- 1.9.1 ^ permalink raw reply related [flat|nested] 49+ messages in thread
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* Re: [PATCH v2 02/18] dt-bindings: timer: sp804: add timer-width property [not found] ` <1457519060-6038-3-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> @ 2016-03-17 17:09 ` Rob Herring 2016-03-17 18:06 ` Robin Murphy 0 siblings, 1 reply; 49+ messages in thread From: Rob Herring @ 2016-03-17 17:09 UTC (permalink / raw) To: Neil Armstrong Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A, tglx-hfZtesqFncYOwBW4kG4KsQ, rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ, sudeep.holla-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA On Wed, Mar 09, 2016 at 11:24:04AM +0100, Neil Armstrong wrote: > Add timer-width optional property to specify a different vendor > specific timer counter bit-width. > > Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> > --- > Documentation/devicetree/bindings/timer/arm,sp804.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/timer/arm,sp804.txt b/Documentation/devicetree/bindings/timer/arm,sp804.txt > index 5cd8eee7..141e143 100644 > --- a/Documentation/devicetree/bindings/timer/arm,sp804.txt > +++ b/Documentation/devicetree/bindings/timer/arm,sp804.txt > @@ -17,6 +17,8 @@ Optional properties: > - arm,sp804-has-irq = <#>: In the case of only 1 timer irq line connected, this > specifies if the irq connection is for timer 1 or timer 2. A value of 1 > or 2 should be used. > +- arm,timer-width: Should contain the width in number of bits of the counter, > + is considered by default 32 but can be changed for vendor variants. That would not be an SP804 nor would the vendor be ARM in that case. So add a new compatible string for the vendor that decided to hack up ARM's IP block. Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 02/18] dt-bindings: timer: sp804: add timer-width property 2016-03-17 17:09 ` Rob Herring @ 2016-03-17 18:06 ` Robin Murphy 2016-03-17 19:00 ` Rob Herring 0 siblings, 1 reply; 49+ messages in thread From: Robin Murphy @ 2016-03-17 18:06 UTC (permalink / raw) To: Rob Herring, Neil Armstrong Cc: devicetree, daniel.lezcano, linux-kernel, sudeep.holla, rmk+kernel, tglx, linux-arm-kernel Hi Rob, On 17/03/16 17:09, Rob Herring wrote: > On Wed, Mar 09, 2016 at 11:24:04AM +0100, Neil Armstrong wrote: >> Add timer-width optional property to specify a different vendor >> specific timer counter bit-width. >> >> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> >> --- >> Documentation/devicetree/bindings/timer/arm,sp804.txt | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/timer/arm,sp804.txt b/Documentation/devicetree/bindings/timer/arm,sp804.txt >> index 5cd8eee7..141e143 100644 >> --- a/Documentation/devicetree/bindings/timer/arm,sp804.txt >> +++ b/Documentation/devicetree/bindings/timer/arm,sp804.txt >> @@ -17,6 +17,8 @@ Optional properties: >> - arm,sp804-has-irq = <#>: In the case of only 1 timer irq line connected, this >> specifies if the irq connection is for timer 1 or timer 2. A value of 1 >> or 2 should be used. >> +- arm,timer-width: Should contain the width in number of bits of the counter, >> + is considered by default 32 but can be changed for vendor variants. > > That would not be an SP804 nor would the vendor be ARM in that case. So > add a new compatible string for the vendor that decided to hack up ARM's > IP block. By all accounts this is some ancient reference design[1] which later evolved _into_ the SP804, so that vendor would probably still be ARM ;) A separate compatible string would indeed make more sense, though. Both semantically and in terms of letting the driver account for the differences automatically. Robin. [1]:http://infocenter.arm.com/help/topic/com.arm.doc.ddi0170a/I350250.html > > Rob > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > ^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 02/18] dt-bindings: timer: sp804: add timer-width property 2016-03-17 18:06 ` Robin Murphy @ 2016-03-17 19:00 ` Rob Herring [not found] ` <CAL_JsqKRjFDNmGjkPfJ-BKXG8ekNzUgear3uLzsFYbZU7Zph7w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 49+ messages in thread From: Rob Herring @ 2016-03-17 19:00 UTC (permalink / raw) To: Robin Murphy Cc: Neil Armstrong, devicetree@vger.kernel.org, Daniel Lezcano, linux-kernel@vger.kernel.org, Sudeep Holla, Russell King, Thomas Gleixner, linux-arm-kernel@lists.infradead.org On Thu, Mar 17, 2016 at 1:06 PM, Robin Murphy <robin.murphy@arm.com> wrote: > Hi Rob, > > On 17/03/16 17:09, Rob Herring wrote: >> >> On Wed, Mar 09, 2016 at 11:24:04AM +0100, Neil Armstrong wrote: >>> >>> Add timer-width optional property to specify a different vendor >>> specific timer counter bit-width. >>> >>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> >>> --- >>> Documentation/devicetree/bindings/timer/arm,sp804.txt | 2 ++ >>> 1 file changed, 2 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/timer/arm,sp804.txt >>> b/Documentation/devicetree/bindings/timer/arm,sp804.txt >>> index 5cd8eee7..141e143 100644 >>> --- a/Documentation/devicetree/bindings/timer/arm,sp804.txt >>> +++ b/Documentation/devicetree/bindings/timer/arm,sp804.txt >>> @@ -17,6 +17,8 @@ Optional properties: >>> - arm,sp804-has-irq = <#>: In the case of only 1 timer irq line >>> connected, this >>> specifies if the irq connection is for timer 1 or timer 2. A >>> value of 1 >>> or 2 should be used. >>> +- arm,timer-width: Should contain the width in number of bits of the >>> counter, >>> + is considered by default 32 but can be changed for vendor >>> variants. >> >> >> That would not be an SP804 nor would the vendor be ARM in that case. So >> add a new compatible string for the vendor that decided to hack up ARM's >> IP block. > > > By all accounts this is some ancient reference design[1] which later evolved > _into_ the SP804, so that vendor would probably still be ARM ;) Right. > A separate compatible string would indeed make more sense, though. Both > semantically and in terms of letting the driver account for the differences > automatically. > > Robin. > > [1]:http://infocenter.arm.com/help/topic/com.arm.doc.ddi0170a/I350250.html Humm, same as integrator timers perhaps? Rob > >> >> Rob >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >> > ^ permalink raw reply [flat|nested] 49+ messages in thread
[parent not found: <CAL_JsqKRjFDNmGjkPfJ-BKXG8ekNzUgear3uLzsFYbZU7Zph7w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH v2 02/18] dt-bindings: timer: sp804: add timer-width property [not found] ` <CAL_JsqKRjFDNmGjkPfJ-BKXG8ekNzUgear3uLzsFYbZU7Zph7w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2016-03-17 19:21 ` Robin Murphy 2016-03-22 9:21 ` Neil Armstrong 0 siblings, 1 reply; 49+ messages in thread From: Robin Murphy @ 2016-03-17 19:21 UTC (permalink / raw) To: Rob Herring Cc: Neil Armstrong, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Daniel Lezcano, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Sudeep Holla, Russell King, Thomas Gleixner, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org On 17/03/16 19:00, Rob Herring wrote: > On Thu, Mar 17, 2016 at 1:06 PM, Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org> wrote: >> Hi Rob, >> >> On 17/03/16 17:09, Rob Herring wrote: >>> >>> On Wed, Mar 09, 2016 at 11:24:04AM +0100, Neil Armstrong wrote: >>>> >>>> Add timer-width optional property to specify a different vendor >>>> specific timer counter bit-width. >>>> >>>> Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> >>>> --- >>>> Documentation/devicetree/bindings/timer/arm,sp804.txt | 2 ++ >>>> 1 file changed, 2 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/timer/arm,sp804.txt >>>> b/Documentation/devicetree/bindings/timer/arm,sp804.txt >>>> index 5cd8eee7..141e143 100644 >>>> --- a/Documentation/devicetree/bindings/timer/arm,sp804.txt >>>> +++ b/Documentation/devicetree/bindings/timer/arm,sp804.txt >>>> @@ -17,6 +17,8 @@ Optional properties: >>>> - arm,sp804-has-irq = <#>: In the case of only 1 timer irq line >>>> connected, this >>>> specifies if the irq connection is for timer 1 or timer 2. A >>>> value of 1 >>>> or 2 should be used. >>>> +- arm,timer-width: Should contain the width in number of bits of the >>>> counter, >>>> + is considered by default 32 but can be changed for vendor >>>> variants. >>> >>> >>> That would not be an SP804 nor would the vendor be ARM in that case. So >>> add a new compatible string for the vendor that decided to hack up ARM's >>> IP block. >> >> >> By all accounts this is some ancient reference design[1] which later evolved >> _into_ the SP804, so that vendor would probably still be ARM ;) > > Right. > >> A separate compatible string would indeed make more sense, though. Both >> semantically and in terms of letting the driver account for the differences >> automatically. >> >> Robin. >> >> [1]:http://infocenter.arm.com/help/topic/com.arm.doc.ddi0170a/I350250.html > > Humm, same as integrator timers perhaps? Having had a quick look, what the Integrator/AP manual describes certainly smells like the same basic block as the "AMBA Timer" - 16 bit counters and the same control register layout - albeit in a mutant triple-timer version with a bigger offset between each register set. Integrator/CP, on the other hand, looks much more SP804-like. Robin. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 02/18] dt-bindings: timer: sp804: add timer-width property 2016-03-17 19:21 ` Robin Murphy @ 2016-03-22 9:21 ` Neil Armstrong 2016-03-22 12:02 ` Robin Murphy 0 siblings, 1 reply; 49+ messages in thread From: Neil Armstrong @ 2016-03-22 9:21 UTC (permalink / raw) To: Robin Murphy, Rob Herring Cc: devicetree@vger.kernel.org, Daniel Lezcano, linux-kernel@vger.kernel.org, Sudeep Holla, Russell King, Thomas Gleixner, linux-arm-kernel@lists.infradead.org On 03/17/2016 08:21 PM, Robin Murphy wrote: > On 17/03/16 19:00, Rob Herring wrote: >> On Thu, Mar 17, 2016 at 1:06 PM, Robin Murphy <robin.murphy@arm.com> wrote: >>> Hi Rob, >>> >>> On 17/03/16 17:09, Rob Herring wrote: >>>> That would not be an SP804 nor would the vendor be ARM in that case. So >>>> add a new compatible string for the vendor that decided to hack up ARM's >>>> IP block. >>> >>> >>> By all accounts this is some ancient reference design[1] which later evolved >>> _into_ the SP804, so that vendor would probably still be ARM ;) >> >> Right. >> >>> A separate compatible string would indeed make more sense, though. Both >>> semantically and in terms of letting the driver account for the differences >>> automatically. >>> >>> Robin. >>> >>> [1]:http://infocenter.arm.com/help/topic/com.arm.doc.ddi0170a/I350250.html >> >> Humm, same as integrator timers perhaps? > > Having had a quick look, what the Integrator/AP manual describes certainly smells like the same basic block as the "AMBA Timer" - 16 bit counters and the same control register layout - albeit in a mutant triple-timer version with a bigger offset between each register set. Integrator/CP, on the other hand, looks much more SP804-like. > > Robin. > Hi, I will switch to oxsemi,ox810se-rps-timer since it need a specific register width that will be handled by the driver. Thanks, Neil ^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 02/18] dt-bindings: timer: sp804: add timer-width property 2016-03-22 9:21 ` Neil Armstrong @ 2016-03-22 12:02 ` Robin Murphy 2016-03-22 14:29 ` Neil Armstrong 0 siblings, 1 reply; 49+ messages in thread From: Robin Murphy @ 2016-03-22 12:02 UTC (permalink / raw) To: Neil Armstrong, Rob Herring Cc: devicetree@vger.kernel.org, Daniel Lezcano, linux-kernel@vger.kernel.org, Sudeep Holla, Russell King, Thomas Gleixner, linux-arm-kernel@lists.infradead.org Hi Neil, On 22/03/16 09:21, Neil Armstrong wrote: > On 03/17/2016 08:21 PM, Robin Murphy wrote: >> On 17/03/16 19:00, Rob Herring wrote: >>> On Thu, Mar 17, 2016 at 1:06 PM, Robin Murphy <robin.murphy@arm.com> wrote: >>>> Hi Rob, >>>> >>>> On 17/03/16 17:09, Rob Herring wrote: >>>>> That would not be an SP804 nor would the vendor be ARM in that case. So >>>>> add a new compatible string for the vendor that decided to hack up ARM's >>>>> IP block. >>>> >>>> >>>> By all accounts this is some ancient reference design[1] which later evolved >>>> _into_ the SP804, so that vendor would probably still be ARM ;) >>> >>> Right. >>> >>>> A separate compatible string would indeed make more sense, though. Both >>>> semantically and in terms of letting the driver account for the differences >>>> automatically. >>>> >>>> Robin. >>>> >>>> [1]:http://infocenter.arm.com/help/topic/com.arm.doc.ddi0170a/I350250.html >>> >>> Humm, same as integrator timers perhaps? >> >> Having had a quick look, what the Integrator/AP manual describes certainly smells like the same basic block as the "AMBA Timer" - 16 bit counters and the same control register layout - albeit in a mutant triple-timer version with a bigger offset between each register set. Integrator/CP, on the other hand, looks much more SP804-like. >> >> Robin. >> > > Hi, > > I will switch to oxsemi,ox810se-rps-timer since it need a specific register width that will be handled by the driver. By "needs a specific register width" do you mean the OxSemi implementation will give a bus error on a 32-bit access and requires 16-bit accessors? If so, I'd expect to see patch 1 changing readl()s to readw()s at least somewhere. Otherwise, if it's merely that the clocksource API needs to know the upper 16 bits of a word it reads are undefined, then since that's the standard behaviour I'd be inclined to add it to the driver as a canonical "arm,amba-timer" implementation, then have your implementation-specific compatible on top of that just in case. Robin. > > Thanks, > Neil > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > ^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 02/18] dt-bindings: timer: sp804: add timer-width property 2016-03-22 12:02 ` Robin Murphy @ 2016-03-22 14:29 ` Neil Armstrong 0 siblings, 0 replies; 49+ messages in thread From: Neil Armstrong @ 2016-03-22 14:29 UTC (permalink / raw) To: Robin Murphy, Rob Herring Cc: devicetree@vger.kernel.org, Daniel Lezcano, linux-kernel@vger.kernel.org, Sudeep Holla, Russell King, Thomas Gleixner, linux-arm-kernel@lists.infradead.org On 03/22/2016 01:02 PM, Robin Murphy wrote: > Hi Neil, >>>> >>>> Humm, same as integrator timers perhaps? >>> >>> Having had a quick look, what the Integrator/AP manual describes certainly smells like the same basic block as the "AMBA Timer" - 16 bit counters and the same control register layout - albeit in a mutant triple-timer version with a bigger offset between each register set. Integrator/CP, on the other hand, looks much more SP804-like. >>> >>> Robin. >>> >> >> Hi, >> >> I will switch to oxsemi,ox810se-rps-timer since it need a specific register width that will be handled by the driver. > > By "needs a specific register width" do you mean the OxSemi implementation will give a bus error on a 32-bit access and requires 16-bit accessors? If so, I'd expect to see patch 1 changing readl()s to readw()s at least somewhere. Otherwise, if it's merely that the clocksource API needs to know the upper 16 bits of a word it reads are undefined, then since that's the standard behaviour I'd be inclined to add it to the driver as a canonical "arm,amba-timer" implementation, then have your implementation-specific compatible on top of that just in case. No actually the bus access is 32bit but the counter is 24bit wide instead of 16bit, so the clocksource won't work and the system time will furiously drift. It's not the case of the clockevent since the delay fits in 24 bits. It also seems is ignores the 32BIT config bit, so it seems based on the initial 16bit only reference design. How do you think I should implement this ? Neil > Robin. > >> >> Thanks, >> Neil >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >> > ^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 04/18] dt-bindings: irq: arm,versatile-fpga: add arm,rps-irq compatible string [not found] ` <1457519060-6038-1-git-send-email-narmstrong@baylibre.com> 2016-03-09 10:24 ` [PATCH v2 02/18] dt-bindings: timer: sp804: add timer-width property Neil Armstrong @ 2016-03-09 10:24 ` Neil Armstrong [not found] ` <1457519060-6038-5-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> 2016-03-09 10:24 ` [PATCH v2 05/18] dt-bindings: vendor-prefixes: Add PLX Technology Neil Armstrong ` (7 subsequent siblings) 9 siblings, 1 reply; 49+ messages in thread From: Neil Armstrong @ 2016-03-09 10:24 UTC (permalink / raw) To: linux-kernel, linux-arm-kernel, tglx, jason, marc.zyngier, devicetree Cc: Neil Armstrong Under the OX810SE, this same controller is used as "Reference Peripheral Specification" Interrupt Controller, so add new compatible string. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- .../devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt index c9cf605..2fe78d5 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt @@ -6,7 +6,7 @@ controllers are OR:ed together and fed to the CPU tile's IRQ input. Each instance can handle up to 32 interrupts. Required properties: -- compatible: "arm,versatile-fpga-irq" +- compatible: "arm,versatile-fpga-irq" or "arm,rps-irq" - interrupt-controller: Identifies the node as an interrupt controller - #interrupt-cells: The number of cells to define the interrupts. Must be 1 as the FPGA IRQ controller has no configuration options for interrupt -- 1.9.1 ^ permalink raw reply related [flat|nested] 49+ messages in thread
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* Re: [PATCH v2 04/18] dt-bindings: irq: arm,versatile-fpga: add arm,rps-irq compatible string [not found] ` <1457519060-6038-5-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> @ 2016-03-17 17:15 ` Rob Herring 0 siblings, 0 replies; 49+ messages in thread From: Rob Herring @ 2016-03-17 17:15 UTC (permalink / raw) To: Neil Armstrong Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, tglx-hfZtesqFncYOwBW4kG4KsQ, jason-NLaQJdtUoK4Be96aLqz0jA, marc.zyngier-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA On Wed, Mar 09, 2016 at 11:24:06AM +0100, Neil Armstrong wrote: > Under the OX810SE, this same controller is used as "Reference Peripheral > Specification" Interrupt Controller, so add new compatible string. > > Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> > --- > .../devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt > index c9cf605..2fe78d5 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt > +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt > @@ -6,7 +6,7 @@ controllers are OR:ed together and fed to the CPU tile's IRQ input. Each > instance can handle up to 32 interrupts. > > Required properties: > -- compatible: "arm,versatile-fpga-irq" > +- compatible: "arm,versatile-fpga-irq" or "arm,rps-irq" Use a compatible string that reflects the actual implementation not a spec. The current string is a bad example as it already refers to multiple implementations. Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 05/18] dt-bindings: vendor-prefixes: Add PLX Technology [not found] ` <1457519060-6038-1-git-send-email-narmstrong@baylibre.com> 2016-03-09 10:24 ` [PATCH v2 02/18] dt-bindings: timer: sp804: add timer-width property Neil Armstrong 2016-03-09 10:24 ` [PATCH v2 04/18] dt-bindings: irq: arm,versatile-fpga: add arm,rps-irq compatible string Neil Armstrong @ 2016-03-09 10:24 ` Neil Armstrong [not found] ` <1457519060-6038-6-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> 2016-03-09 10:24 ` [PATCH v2 06/18] dt-bindings: Add Oxford Semiconductors to vendor prefixes Neil Armstrong ` (6 subsequent siblings) 9 siblings, 1 reply; 49+ messages in thread From: Neil Armstrong @ 2016-03-09 10:24 UTC (permalink / raw) To: linux-kernel, linux-arm-kernel, devicetree; +Cc: Neil Armstrong Add PLX Technology vendor prefix. Fixed "pixdir" alphabetizing. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- Documentation/devicetree/bindings/vendor-prefixes.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 72e2c5a..8c084c1 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -175,9 +175,10 @@ parade Parade Technologies Inc. pericom Pericom Technology Inc. phytec PHYTEC Messtechnik GmbH picochip Picochip Ltd +pixcir PIXCIR MICROELECTRONICS Co., Ltd plathome Plat'Home Co., Ltd. plda PLDA -pixcir PIXCIR MICROELECTRONICS Co., Ltd +plxtech PLX Technology, Inc. pulsedlight PulsedLight, Inc powervr PowerVR (deprecated, use img) qca Qualcomm Atheros, Inc. -- 1.9.1 ^ permalink raw reply related [flat|nested] 49+ messages in thread
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* Re: [PATCH v2 05/18] dt-bindings: vendor-prefixes: Add PLX Technology [not found] ` <1457519060-6038-6-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> @ 2016-03-17 17:15 ` Rob Herring 0 siblings, 0 replies; 49+ messages in thread From: Rob Herring @ 2016-03-17 17:15 UTC (permalink / raw) To: Neil Armstrong Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA On Wed, Mar 09, 2016 at 11:24:07AM +0100, Neil Armstrong wrote: > Add PLX Technology vendor prefix. > Fixed "pixdir" alphabetizing. > > Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> > --- > Documentation/devicetree/bindings/vendor-prefixes.txt | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 06/18] dt-bindings: Add Oxford Semiconductors to vendor prefixes [not found] ` <1457519060-6038-1-git-send-email-narmstrong@baylibre.com> ` (2 preceding siblings ...) 2016-03-09 10:24 ` [PATCH v2 05/18] dt-bindings: vendor-prefixes: Add PLX Technology Neil Armstrong @ 2016-03-09 10:24 ` Neil Armstrong 2016-03-17 17:16 ` Rob Herring 2016-03-09 10:24 ` [PATCH v2 08/18] dt-bindings: Add PLX Technology Reset Controller bindings Neil Armstrong ` (5 subsequent siblings) 9 siblings, 1 reply; 49+ messages in thread From: Neil Armstrong @ 2016-03-09 10:24 UTC (permalink / raw) To: linux-kernel, linux-arm-kernel, devicetree; +Cc: Neil Armstrong Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 8c084c1..188671f 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -170,6 +170,7 @@ opencores OpenCores.org option Option NV ortustech Ortus Technology Co., Ltd. ovti OmniVision Technologies +oxsemi Oxford Semiconductors, Ltd. panasonic Panasonic Corporation parade Parade Technologies Inc. pericom Pericom Technology Inc. -- 1.9.1 ^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [PATCH v2 06/18] dt-bindings: Add Oxford Semiconductors to vendor prefixes 2016-03-09 10:24 ` [PATCH v2 06/18] dt-bindings: Add Oxford Semiconductors to vendor prefixes Neil Armstrong @ 2016-03-17 17:16 ` Rob Herring 0 siblings, 0 replies; 49+ messages in thread From: Rob Herring @ 2016-03-17 17:16 UTC (permalink / raw) To: Neil Armstrong; +Cc: linux-kernel, linux-arm-kernel, devicetree On Wed, Mar 09, 2016 at 11:24:08AM +0100, Neil Armstrong wrote: > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + > 1 file changed, 1 insertion(+) Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 08/18] dt-bindings: Add PLX Technology Reset Controller bindings [not found] ` <1457519060-6038-1-git-send-email-narmstrong@baylibre.com> ` (3 preceding siblings ...) 2016-03-09 10:24 ` [PATCH v2 06/18] dt-bindings: Add Oxford Semiconductors to vendor prefixes Neil Armstrong @ 2016-03-09 10:24 ` Neil Armstrong [not found] ` <1457519060-6038-9-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> 2016-03-09 10:24 ` [PATCH v2 10/18] dt-bindings: Add PLX Technology OXNAS Standard Clocks bindings Neil Armstrong ` (4 subsequent siblings) 9 siblings, 1 reply; 49+ messages in thread From: Neil Armstrong @ 2016-03-09 10:24 UTC (permalink / raw) To: linux-kernel, linux-arm-kernel, p.zabel, devicetree; +Cc: Neil Armstrong Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- .../devicetree/bindings/reset/plxtech,reset.txt | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/plxtech,reset.txt diff --git a/Documentation/devicetree/bindings/reset/plxtech,reset.txt b/Documentation/devicetree/bindings/reset/plxtech,reset.txt new file mode 100644 index 0000000..581c974 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/plxtech,reset.txt @@ -0,0 +1,58 @@ +PLX Technology OXNAS SoC Family RESET Controller +================================================ + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be "oxsemi,ox810se-reset" +- #reset-cells: 1, see below + +Parent node should have the following properties : +- compatible: Should be "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd" + +For OX810SE, the indices are : + - 0 : ARM + - 1 : COPRO + - 2 : Reserved + - 3 : Reserved + - 4 : USBHS + - 5 : USBHSPHY + - 6 : MAC + - 7 : PCI + - 8 : DMA + - 9 : DPE + - 10 : DDR + - 11 : SATA + - 12 : SATA_LINK + - 13 : SATA_PHY + - 14 : Reserved + - 15 : NAND + - 16 : GPIO + - 17 : UART1 + - 18 : UART2 + - 19 : MISC + - 20 : I2S + - 21 : AHB_MON + - 22 : UART3 + - 23 : UART4 + - 24 : SGDMA + - 25 : Reserved + - 26 : Reserved + - 27 : Reserved + - 28 : Reserved + - 29 : Reserved + - 30 : Reserved + - 31 : BUS + +example: + +sys: sys-ctrl@000000 { + compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"; + reg = <0x000000 0x100000>; + + reset: reset-controller { + compatible = "oxsemi,ox810se-reset"; + #reset-cells = <1>; + }; +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 49+ messages in thread
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* Re: [PATCH v2 08/18] dt-bindings: Add PLX Technology Reset Controller bindings [not found] ` <1457519060-6038-9-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> @ 2016-03-17 17:18 ` Rob Herring 0 siblings, 0 replies; 49+ messages in thread From: Rob Herring @ 2016-03-17 17:18 UTC (permalink / raw) To: Neil Armstrong Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ, devicetree-u79uwXL29TY76Z2rM5mHXA On Wed, Mar 09, 2016 at 11:24:10AM +0100, Neil Armstrong wrote: > Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> > --- > .../devicetree/bindings/reset/plxtech,reset.txt | 58 ++++++++++++++++++++++ > 1 file changed, 58 insertions(+) > create mode 100644 Documentation/devicetree/bindings/reset/plxtech,reset.txt Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 10/18] dt-bindings: Add PLX Technology OXNAS Standard Clocks bindings [not found] ` <1457519060-6038-1-git-send-email-narmstrong@baylibre.com> ` (4 preceding siblings ...) 2016-03-09 10:24 ` [PATCH v2 08/18] dt-bindings: Add PLX Technology Reset Controller bindings Neil Armstrong @ 2016-03-09 10:24 ` Neil Armstrong 2016-03-17 17:19 ` Rob Herring 2016-03-09 10:24 ` [PATCH v2 12/18] dt-bindings: Add PLX Technology OXNAS pinctrl and gpio bindings Neil Armstrong ` (3 subsequent siblings) 9 siblings, 1 reply; 49+ messages in thread From: Neil Armstrong @ 2016-03-09 10:24 UTC (permalink / raw) To: linux-kernel, linux-arm-kernel, linux-clk, devicetree; +Cc: Neil Armstrong Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- .../devicetree/bindings/clock/plxtech,stdclk.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/plxtech,stdclk.txt diff --git a/Documentation/devicetree/bindings/clock/plxtech,stdclk.txt b/Documentation/devicetree/bindings/clock/plxtech,stdclk.txt new file mode 100644 index 0000000..c60b459 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/plxtech,stdclk.txt @@ -0,0 +1,35 @@ +PLX Technology OXNAS SoC Family Standard Clocks +================================================ + +Please also refer to clock-bindings.txt in this directory for common clock +bindings usage. + +Required properties: +- compatible: Should be "oxsemi,ox810se-stdclk" +- #clock-cells: 1, see below + +Parent node should have the following properties : +- compatible: Should be "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd" + +For OX810SE, the clock indices are : + - 0: LEON + - 1: DMA_SGDMA + - 2: CIPHER + - 3: SATA + - 4: AUDIO + - 5: USBMPH + - 6: ETHA + - 7: PCIA + - 8: NAND + +example: + +sys: sys-ctrl@000000 { + compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"; + reg = <0x000000 0x100000>; + + stdclk: stdclk { + compatible = "oxsemi,ox810se-stdclk"; + #clock-cells = <1>; + }; +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [PATCH v2 10/18] dt-bindings: Add PLX Technology OXNAS Standard Clocks bindings 2016-03-09 10:24 ` [PATCH v2 10/18] dt-bindings: Add PLX Technology OXNAS Standard Clocks bindings Neil Armstrong @ 2016-03-17 17:19 ` Rob Herring 0 siblings, 0 replies; 49+ messages in thread From: Rob Herring @ 2016-03-17 17:19 UTC (permalink / raw) To: Neil Armstrong; +Cc: linux-kernel, linux-arm-kernel, linux-clk, devicetree On Wed, Mar 09, 2016 at 11:24:12AM +0100, Neil Armstrong wrote: > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > .../devicetree/bindings/clock/plxtech,stdclk.txt | 35 ++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/plxtech,stdclk.txt Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 12/18] dt-bindings: Add PLX Technology OXNAS pinctrl and gpio bindings [not found] ` <1457519060-6038-1-git-send-email-narmstrong@baylibre.com> ` (5 preceding siblings ...) 2016-03-09 10:24 ` [PATCH v2 10/18] dt-bindings: Add PLX Technology OXNAS Standard Clocks bindings Neil Armstrong @ 2016-03-09 10:24 ` Neil Armstrong 2016-03-17 17:25 ` Rob Herring [not found] ` <1457519060-6038-1-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> ` (2 subsequent siblings) 9 siblings, 1 reply; 49+ messages in thread From: Neil Armstrong @ 2016-03-09 10:24 UTC (permalink / raw) To: linux-kernel, linux-arm-kernel, linus.walleij, linux-gpio, devicetree Cc: Neil Armstrong Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- .../devicetree/bindings/gpio/gpio_oxnas.txt | 27 ++++++ .../bindings/pinctrl/plxtech,pinctrl.txt | 100 +++++++++++++++++++++ 2 files changed, 127 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio_oxnas.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt diff --git a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt new file mode 100644 index 0000000..cbb03c4 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt @@ -0,0 +1,27 @@ +PLX Technology OXNAS SoC GPIO Controller +========================================== + +Required properties: +- compatible: "oxsemi,ox810se-gpio". +- reg: Should contain GPIO controller registers location and length +- interrupts: Should be the port interrupt shared by all the pins. +- #gpio-cells: Should be two. The first cell is the pin number and + the second cell is used to specify optional parameters (currently + unused). +- gpio-controller: Marks the device node as a GPIO controller. + +optional properties: +- #gpio-lines: Number of gpio if absent 32. + + +Example: + gpio0: gpio@000000 { + compatible = "oxsemi,ox810se-gpio"; + reg = <0x000000 0x100000>; + interrupts = <21>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-lines = <32>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt new file mode 100644 index 0000000..0c5051a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt @@ -0,0 +1,100 @@ +PLX Technology OXNAS SoC Pinmux Controller +========================================== + +The OXNAS Pinmux Controller, enables the IC to share one PAD to several +functional blocks. The sharing is done by multiplexing the PAD input/output +signals. For each PAD there are up to 8 muxing options (called periph modes). +Since different modules require different PAD settings +(like pull up, keeper, etc) the contoller controls also the PAD settings +parameters. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +OXNAS pin configuration node is a node of a group of pins which can be +used for a specific device or function. This node represents both mux and config +of the pins in that group. The 'pins' selects the function mode(also named pin +mode) this pin can work on and the 'config' configures various pad settings +such as pull-up, multi drive, etc. + +Required properties for iomux controller: +- compatible: "oxsemi,ox810se-pinctrl" +- plxtech,mux-mask: array of mask (periph per bank) to describe if a pin can be + configured in this periph mode. All the periph and bank need to be describe. +- plxtech,sys-ctrl: a phandle to the system controller syscon node + +How to create such array: + +Each column will represent the possible peripheral of the pinctrl +Each line will represent a pio bank + +For example : +Peripheral: 2 ( A and B) +Bank: 2 (A, B and C) +=> + + /* A B */ + 0xffffffff 0xffc00c3b /* pioA */ + 0xffffffff 0x7fff3ccf /* pioB */ + +For each peripheral/bank we will descibe in a u32 if a pin can be +configured in it by putting 1 to the pin bit (1 << pin) + +Required properties for pin configuration node: +- plxtech,pins: 4 integers array, represents a group of pins mux and config + setting. The format is plxtech,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>. + The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B... + PIN_BANK 0 is pioA, PIN_BANK 1 is pioB... + +Bits used for CONFIG: + - None Yet + +Examples: + +pinctrl: pinctrl { + compatible = "oxsemi,ox810se-pinctrl", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Regmap for sys registers */ + plxtech,sys-ctrl = <&sys>; + + /* Default, all-open mux-map */ + plxtech,mux-mask = < + 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF + >; + + uart0 { + pinctrl_uart0: uart0 { + plxtech,pins = <0 31 3 0 + 0 32 3 0>; + }; + pinctrl_uart0_modem: uart0_modem { + plxtech,pins = <0 27 3 0 + 0 28 3 0 + 0 29 3 0 + 0 30 3 0 + 0 33 3 0 + 0 34 3 0>; + }; + }; +}; + +uart0: uart@200000 { + compatible = "ns16550a"; + reg = <0x200000 0x100000>; + clocks = <&sysclk>; + interrupts = <23>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 17>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; +}; -- 1.9.1 ^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [PATCH v2 12/18] dt-bindings: Add PLX Technology OXNAS pinctrl and gpio bindings 2016-03-09 10:24 ` [PATCH v2 12/18] dt-bindings: Add PLX Technology OXNAS pinctrl and gpio bindings Neil Armstrong @ 2016-03-17 17:25 ` Rob Herring 0 siblings, 0 replies; 49+ messages in thread From: Rob Herring @ 2016-03-17 17:25 UTC (permalink / raw) To: Neil Armstrong Cc: linux-kernel, linux-arm-kernel, linus.walleij, linux-gpio, devicetree On Wed, Mar 09, 2016 at 11:24:14AM +0100, Neil Armstrong wrote: > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > .../devicetree/bindings/gpio/gpio_oxnas.txt | 27 ++++++ > .../bindings/pinctrl/plxtech,pinctrl.txt | 100 +++++++++++++++++++++ > 2 files changed, 127 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpio/gpio_oxnas.txt > create mode 100644 Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt > > diff --git a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt > new file mode 100644 > index 0000000..cbb03c4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt > @@ -0,0 +1,27 @@ > +PLX Technology OXNAS SoC GPIO Controller > +========================================== > + > +Required properties: > +- compatible: "oxsemi,ox810se-gpio". > +- reg: Should contain GPIO controller registers location and length > +- interrupts: Should be the port interrupt shared by all the pins. > +- #gpio-cells: Should be two. The first cell is the pin number and > + the second cell is used to specify optional parameters (currently > + unused). > +- gpio-controller: Marks the device node as a GPIO controller. > + > +optional properties: > +- #gpio-lines: Number of gpio if absent 32. > + > + > +Example: > + gpio0: gpio@000000 { Drop the leading 0s. > + compatible = "oxsemi,ox810se-gpio"; > + reg = <0x000000 0x100000>; > + interrupts = <21>; > + #gpio-cells = <2>; > + gpio-controller; > + interrupt-controller; > + #interrupt-cells = <2>; > + #gpio-lines = <32>; > + }; > diff --git a/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt > new file mode 100644 > index 0000000..0c5051a > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/plxtech,pinctrl.txt > @@ -0,0 +1,100 @@ > +PLX Technology OXNAS SoC Pinmux Controller > +========================================== > + > +The OXNAS Pinmux Controller, enables the IC to share one PAD to several > +functional blocks. The sharing is done by multiplexing the PAD input/output > +signals. For each PAD there are up to 8 muxing options (called periph modes). > +Since different modules require different PAD settings > +(like pull up, keeper, etc) the contoller controls also the PAD settings > +parameters. > + > +Please refer to pinctrl-bindings.txt in this directory for details of the > +common pinctrl bindings used by client devices, including the meaning of the > +phrase "pin configuration node". > + > +OXNAS pin configuration node is a node of a group of pins which can be > +used for a specific device or function. This node represents both mux and config > +of the pins in that group. The 'pins' selects the function mode(also named pin > +mode) this pin can work on and the 'config' configures various pad settings > +such as pull-up, multi drive, etc. > + > +Required properties for iomux controller: > +- compatible: "oxsemi,ox810se-pinctrl" > +- plxtech,mux-mask: array of mask (periph per bank) to describe if a pin can be > + configured in this periph mode. All the periph and bank need to be describe. > +- plxtech,sys-ctrl: a phandle to the system controller syscon node > + > +How to create such array: > + > +Each column will represent the possible peripheral of the pinctrl > +Each line will represent a pio bank > + > +For example : > +Peripheral: 2 ( A and B) > +Bank: 2 (A, B and C) > +=> > + > + /* A B */ > + 0xffffffff 0xffc00c3b /* pioA */ > + 0xffffffff 0x7fff3ccf /* pioB */ > + > +For each peripheral/bank we will descibe in a u32 if a pin can be > +configured in it by putting 1 to the pin bit (1 << pin) > + > +Required properties for pin configuration node: > +- plxtech,pins: 4 integers array, represents a group of pins mux and config > + setting. The format is plxtech,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>. > + The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B... > + PIN_BANK 0 is pioA, PIN_BANK 1 is pioB... > + > +Bits used for CONFIG: > + - None Yet > + > +Examples: > + > +pinctrl: pinctrl { > + compatible = "oxsemi,ox810se-pinctrl", "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + /* Regmap for sys registers */ > + plxtech,sys-ctrl = <&sys>; > + > + /* Default, all-open mux-map */ > + plxtech,mux-mask = < > + 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF > + 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF > + >; > + > + uart0 { > + pinctrl_uart0: uart0 { > + plxtech,pins = <0 31 3 0 > + 0 32 3 0>; > + }; > + pinctrl_uart0_modem: uart0_modem { > + plxtech,pins = <0 27 3 0 > + 0 28 3 0 > + 0 29 3 0 > + 0 30 3 0 > + 0 33 3 0 > + 0 34 3 0>; > + }; > + }; > +}; > + > +uart0: uart@200000 { serial@200000 With those changes: Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 49+ messages in thread
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* [PATCH v2 15/18] arm: boot: dts: Add PLX Technology OX810SE dtsi [not found] ` <1457519060-6038-1-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> @ 2016-03-09 10:24 ` Neil Armstrong 2016-03-09 10:24 ` [PATCH v2 18/18] arm: boot: dts: Add Western Digital My Book World Edition device tree Neil Armstrong 1 sibling, 0 replies; 49+ messages in thread From: Neil Armstrong @ 2016-03-09 10:24 UTC (permalink / raw) To: linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-lFZ/pmaqli7XmaaqVzeoHQ Cc: Neil Armstrong Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> --- arch/arm/boot/dts/ox810se.dtsi | 273 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 273 insertions(+) create mode 100644 arch/arm/boot/dts/ox810se.dtsi diff --git a/arch/arm/boot/dts/ox810se.dtsi b/arch/arm/boot/dts/ox810se.dtsi new file mode 100644 index 0000000..5852a57 --- /dev/null +++ b/arch/arm/boot/dts/ox810se.dtsi @@ -0,0 +1,273 @@ +/* + * ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC + * + * Copyright (C) 2016 Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> + * + * Licensed under GPLv2 or later + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "oxsemi,ox810se"; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + clocks = <&armclk>; + }; + }; + + memory { + /* Max 256MB @ 0x48000000 */ + reg = <0x48000000 0x10000000>; + }; + + clocks { + osc: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + gmacclk: gmacclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + rpsclk: rpsclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&osc>; + }; + + pll400: pll400 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <733333333>; + }; + + sysclk: sysclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clocks = <&pll400>; + }; + + armclk: armclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clocks = <&pll400>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&intc>; + + apb-bridge@44000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x44000000 0x1000000>; + + pinctrl: pinctrl { + compatible = "oxsemi,ox810se-pinctrl", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Regmap for sys registers */ + plxtech,sys-ctrl = <&sys>; + + /* Default, all-open mux-map */ + plxtech,mux-mask = < + 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF + >; + + gpio0: gpio@000000 { + compatible = "oxsemi,ox810se-gpio"; + reg = <0x000000 0x100000>; + interrupts = <21>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-lines = <32>; + }; + + gpio1: gpio@100000 { + compatible = "oxsemi,ox810se-gpio"; + reg = <0x100000 0x100000>; + interrupts = <22>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-lines = <3>; + }; + + uart0 { + pinctrl_uart0: uart0 { + plxtech,pins = <0 31 3 0 + 0 32 3 0>; + }; + pinctrl_uart0_modem: uart0_modem { + plxtech,pins = <0 27 3 0 + 0 28 3 0 + 0 29 3 0 + 0 30 3 0 + 0 33 3 0 + 0 34 3 0>; + }; + }; + + uart1 { + pinctrl_uart1: uart1 { + plxtech,pins = <0 20 3 0 + 0 22 3 0>; + }; + pinctrl_uart1_modem: uart1_modem { + plxtech,pins = <0 8 3 0 + 0 9 3 0 + 0 23 3 0 + 0 24 3 0 + 0 25 3 0 + 0 26 3 0>; + }; + }; + + uart2 { + pinctrl_uart2: uart2 { + plxtech,pins = <0 6 3 0 + 0 7 3 0>; + }; + pinctrl_uart2_modem: uart2_modem { + plxtech,pins = <0 0 3 0 + 0 1 3 0 + 0 2 3 0 + 0 3 3 0 + 0 4 3 0 + 0 5 3 0>; + }; + }; + }; + + uart0: serial@200000 { + compatible = "ns16550a"; + reg = <0x200000 0x100000>; + clocks = <&sysclk>; + interrupts = <23>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 17>; + }; + + uart1: serial@300000 { + compatible = "ns16550a"; + reg = <0x300000 0x100000>; + clocks = <&sysclk>; + interrupts = <24>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 18>; + }; + + uart2: serial@900000 { + compatible = "ns16550a"; + reg = <0x900000 0x100000>; + clocks = <&sysclk>; + interrupts = <29>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 22>; + }; + + uart3: serial@a00000 { + compatible = "ns16550a"; + reg = <0xa00000 0x100000>; + clocks = <&sysclk>; + interrupts = <30>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 23>; + }; + }; + + apb-bridge@45000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x45000000 0x1000000>; + + sys: sys-ctrl@000000 { + compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"; + reg = <0x000000 0x100000>; + + reset: reset-controller { + compatible = "oxsemi,ox810se-reset"; + #reset-cells = <1>; + }; + + stdclk: stdclk { + compatible = "oxsemi,ox810se-stdclk"; + #clock-cells = <1>; + }; + }; + + rps@300000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x300000 0x100000>; + + intc: interrupt-controller@0 { + compatible = "arm,rps-irq"; + interrupt-controller; + reg = <0 0x200>; + #interrupt-cells = <1>; + valid-mask = <0xFFFFFFFF>; + clear-mask = <0>; + }; + + timer0: timer@200 { + compatible = "arm,sp804"; + reg = <0x200 0x40>; + clocks = <&rpsclk>; + interrupts = <4 5>; + arm,timer-width = <24>; + }; + }; + }; + }; +}; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 18/18] arm: boot: dts: Add Western Digital My Book World Edition device tree [not found] ` <1457519060-6038-1-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> 2016-03-09 10:24 ` [PATCH v2 15/18] arm: boot: dts: Add PLX Technology OX810SE dtsi Neil Armstrong @ 2016-03-09 10:24 ` Neil Armstrong 1 sibling, 0 replies; 49+ messages in thread From: Neil Armstrong @ 2016-03-09 10:24 UTC (permalink / raw) To: linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-lFZ/pmaqli7XmaaqVzeoHQ Cc: Neil Armstrong Add Western Digital My Book World Edition device tree based on PLX Technology OX810SE SoC. Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/wd-mbwe.dts | 112 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 114 insertions(+) create mode 100644 arch/arm/boot/dts/wd-mbwe.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a4a6d70..0395674 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -520,6 +520,8 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ orion5x-rd88f5182-nas.dtb dtb-$(CONFIG_ARCH_PRIMA2) += \ prima2-evb.dtb +dtb-$(CONFIG_ARCH_OXNAS) += \ + wd-mbwe.dtb dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8064-cm-qs600.dtb \ qcom-apq8064-ifc6410.dtb \ diff --git a/arch/arm/boot/dts/wd-mbwe.dts b/arch/arm/boot/dts/wd-mbwe.dts new file mode 100644 index 0000000..ac3250a --- /dev/null +++ b/arch/arm/boot/dts/wd-mbwe.dts @@ -0,0 +1,112 @@ +/* + * wd-mbwe.dtsi - Device tree file for Western Digital My Book World Edition + * + * Copyright (C) 2016 Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> + * + * Licensed under GPLv2 or later + */ + +/dts-v1/; +#include "ox810se.dtsi" + +/ { + model = "Western Digital My Book World Edition"; + + compatible = "wd,mbwe", "oxsemi,ox810se"; + + chosen { + bootargs = "console=ttyS1,115200n8 earlyprintk=serial"; + }; + + memory { + /* 128Mbytes DDR */ + reg = <0x48000000 0x8000000>; + }; + + aliases { + serial1 = &uart1; + gpio0 = &gpio0; + gpio1 = &gpio1; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + power { + label = "power"; + gpios = <&gpio0 0 1>; + linux,code = <0x198>; + }; + + recovery { + label = "recovery"; + gpios = <&gpio0 4 1>; + linux,code = <0xab>; + }; + }; + + leds { + compatible = "gpio-leds"; + + a0 { + label = "activity0"; + gpios = <&gpio0 25 0>; + default-state = "keep"; + }; + + a1 { + label = "activity1"; + gpios = <&gpio0 26 0>; + default-state = "keep"; + }; + + a2 { + label = "activity2"; + gpios = <&gpio0 5 0>; + default-state = "keep"; + }; + + a3 { + label = "activity3"; + gpios = <&gpio0 6 0>; + default-state = "keep"; + }; + + a4 { + label = "activity4"; + gpios = <&gpio0 7 0>; + default-state = "keep"; + }; + + a5 { + label = "activity5"; + gpios = <&gpio1 2 0>; + default-state = "keep"; + }; + }; + + i2c-gpio { + compatible = "i2c-gpio"; + gpios = <&gpio0 3 0 /* sda */ + &gpio0 2 0 /* scl */ + >; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + + rtc0: rtc@48 { + compatible = "st,m41t00"; + reg = <0x68>; + }; + }; +}; + +&uart1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v2 16/18] dt-bindings: Add OXNAS bindings [not found] ` <1457519060-6038-1-git-send-email-narmstrong@baylibre.com> ` (7 preceding siblings ...) [not found] ` <1457519060-6038-1-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> @ 2016-03-09 10:24 ` Neil Armstrong [not found] ` <1457519060-6038-17-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> 2016-03-09 10:24 ` [PATCH v2 17/18] dt-bindings: Add Western Digital to vendor prefixes Neil Armstrong 9 siblings, 1 reply; 49+ messages in thread From: Neil Armstrong @ 2016-03-09 10:24 UTC (permalink / raw) To: linux-kernel, linux-arm-kernel, devicetree; +Cc: Neil Armstrong Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- Documentation/devicetree/bindings/arm/oxnas.txt | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/oxnas.txt diff --git a/Documentation/devicetree/bindings/arm/oxnas.txt b/Documentation/devicetree/bindings/arm/oxnas.txt new file mode 100644 index 0000000..f6032d2 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/oxnas.txt @@ -0,0 +1,9 @@ +PLX Technology OXNAS SoCs Family device tree bindings +------------------------------------------- + +Boards with the OX810SE Soc SoC shall have the following properties: + Required root node property: + compatible: "oxsemi,ox810se" + +Board compatible values: + - "wd,mbwe" (OX810SE) -- 1.9.1 ^ permalink raw reply related [flat|nested] 49+ messages in thread
[parent not found: <1457519060-6038-17-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>]
* Re: [PATCH v2 16/18] dt-bindings: Add OXNAS bindings [not found] ` <1457519060-6038-17-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> @ 2016-03-17 17:27 ` Rob Herring 2016-03-23 8:37 ` Neil Armstrong 0 siblings, 1 reply; 49+ messages in thread From: Rob Herring @ 2016-03-17 17:27 UTC (permalink / raw) To: Neil Armstrong Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA On Wed, Mar 09, 2016 at 11:24:18AM +0100, Neil Armstrong wrote: > Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> > --- > Documentation/devicetree/bindings/arm/oxnas.txt | 9 +++++++++ > 1 file changed, 9 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/oxnas.txt > > diff --git a/Documentation/devicetree/bindings/arm/oxnas.txt b/Documentation/devicetree/bindings/arm/oxnas.txt > new file mode 100644 > index 0000000..f6032d2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/oxnas.txt > @@ -0,0 +1,9 @@ > +PLX Technology OXNAS SoCs Family device tree bindings > +------------------------------------------- > + > +Boards with the OX810SE Soc SoC shall have the following properties: s/Soc SoC/SoC/ > + Required root node property: > + compatible: "oxsemi,ox810se" > + > +Board compatible values: > + - "wd,mbwe" (OX810SE) Seems kind of generic. Only one version? > -- > 1.9.1 > > -- > To unsubscribe from this list: send the line "unsubscribe devicetree" in > the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 16/18] dt-bindings: Add OXNAS bindings 2016-03-17 17:27 ` Rob Herring @ 2016-03-23 8:37 ` Neil Armstrong 0 siblings, 0 replies; 49+ messages in thread From: Neil Armstrong @ 2016-03-23 8:37 UTC (permalink / raw) To: Rob Herring; +Cc: linux-kernel, linux-arm-kernel, devicetree On 03/17/2016 06:27 PM, Rob Herring wrote: > On Wed, Mar 09, 2016 at 11:24:18AM +0100, Neil Armstrong wrote: >> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> >> --- >> Documentation/devicetree/bindings/arm/oxnas.txt | 9 +++++++++ >> 1 file changed, 9 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/arm/oxnas.txt >> >> diff --git a/Documentation/devicetree/bindings/arm/oxnas.txt b/Documentation/devicetree/bindings/arm/oxnas.txt >> new file mode 100644 >> index 0000000..f6032d2 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/oxnas.txt >> @@ -0,0 +1,9 @@ >> +PLX Technology OXNAS SoCs Family device tree bindings >> +------------------------------------------- >> + >> +Boards with the OX810SE Soc SoC shall have the following properties: > > s/Soc SoC/SoC/ OK > >> + Required root node property: >> + compatible: "oxsemi,ox810se" >> + >> +Board compatible values: >> + - "wd,mbwe" (OX810SE) > > Seems kind of generic. Only one version? There is a My Book World Edition II, which seems to be the same (they share the same firmware) but with two SATA ports, the original kernel does not make any differences between the two models. I'm not aware of different versions and the firmware does not contain any specific code for different board revisions. Neil ^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 17/18] dt-bindings: Add Western Digital to vendor prefixes [not found] ` <1457519060-6038-1-git-send-email-narmstrong@baylibre.com> ` (8 preceding siblings ...) 2016-03-09 10:24 ` [PATCH v2 16/18] dt-bindings: Add OXNAS bindings Neil Armstrong @ 2016-03-09 10:24 ` Neil Armstrong 9 siblings, 0 replies; 49+ messages in thread From: Neil Armstrong @ 2016-03-09 10:24 UTC (permalink / raw) To: linux-kernel, linux-arm-kernel, devicetree; +Cc: Neil Armstrong Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 188671f..968d3f4 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -249,6 +249,7 @@ via VIA Technologies, Inc. virtio Virtual I/O Device Specification, developed by the OASIS consortium vivante Vivante Corporation voipac Voipac Technologies s.r.o. +wd Western Digital Corp. wexler Wexler winbond Winbond Electronics corp. wlf Wolfson Microelectronics -- 1.9.1 ^ permalink raw reply related [flat|nested] 49+ messages in thread
end of thread, other threads:[~2016-03-23 8:37 UTC | newest]
Thread overview: 49+ messages (download: mbox.gz follow: Atom feed
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[not found] <1457005210-18485-1-git-send-email-narmstrong@baylibre.com>
[not found] ` <1457005210-18485-1-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
2016-03-03 11:39 ` [PATCH 01/17] dt-bindings: vendor-prefixes: Add PLX Technology Neil Armstrong
2016-03-03 15:02 ` Philipp Zabel
2016-03-05 4:29 ` Rob Herring
2016-03-07 9:55 ` Philipp Zabel
2016-03-03 11:40 ` [PATCH 14/17] arm: boot: dts: Add PLX Technology OX810SE dtsi Neil Armstrong
2016-03-03 12:15 ` Arnd Bergmann
2016-03-03 13:39 ` Neil Armstrong
2016-03-03 11:39 ` [PATCH 03/17] dt-bindings: Add PLX Technology RPS IRQ Controller bindings Neil Armstrong
2016-03-03 14:53 ` Andrew Lunn
2016-03-03 14:57 ` Neil Armstrong
[not found] ` <56D850C6.1010404-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
2016-03-03 15:06 ` Andrew Lunn
2016-03-03 11:39 ` [PATCH 05/17] dt-bindings: Add PLX Technology RPS Timer bindings Neil Armstrong
2016-03-03 11:40 ` [PATCH 07/17] dt-bindings: Add PLX Technology Reset Controller bindings Neil Armstrong
2016-03-03 14:21 ` Philipp Zabel
[not found] ` <1457014907.3425.56.camel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
2016-03-03 14:24 ` Neil Armstrong
2016-03-03 14:31 ` Philipp Zabel
2016-03-03 11:40 ` [PATCH 09/17] dt-bindings: Add PLX Technology OXNAS Standard Clocks bindings Neil Armstrong
2016-03-03 11:40 ` [PATCH 11/17] dt-bindings: Add PLX Technology OXNAS pinctrl and gpio bindings Neil Armstrong
[not found] ` <1457005210-18485-12-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
2016-03-15 14:30 ` Linus Walleij
2016-03-03 11:40 ` [PATCH 15/17] dt-bindings: Add OXNAS bindings Neil Armstrong
2016-03-03 11:40 ` [PATCH 16/17] dt-bindings: Add Western Digital to vendor prefixes Neil Armstrong
2016-03-05 4:29 ` Rob Herring
2016-03-03 11:40 ` [PATCH 17/17] arm: boot: dts: Add Western Digital My Book World Edition device tree Neil Armstrong
[not found] ` <1457519060-6038-1-git-send-email-narmstrong@baylibre.com>
2016-03-09 10:24 ` [PATCH v2 02/18] dt-bindings: timer: sp804: add timer-width property Neil Armstrong
[not found] ` <1457519060-6038-3-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
2016-03-17 17:09 ` Rob Herring
2016-03-17 18:06 ` Robin Murphy
2016-03-17 19:00 ` Rob Herring
[not found] ` <CAL_JsqKRjFDNmGjkPfJ-BKXG8ekNzUgear3uLzsFYbZU7Zph7w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-03-17 19:21 ` Robin Murphy
2016-03-22 9:21 ` Neil Armstrong
2016-03-22 12:02 ` Robin Murphy
2016-03-22 14:29 ` Neil Armstrong
2016-03-09 10:24 ` [PATCH v2 04/18] dt-bindings: irq: arm,versatile-fpga: add arm,rps-irq compatible string Neil Armstrong
[not found] ` <1457519060-6038-5-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
2016-03-17 17:15 ` Rob Herring
2016-03-09 10:24 ` [PATCH v2 05/18] dt-bindings: vendor-prefixes: Add PLX Technology Neil Armstrong
[not found] ` <1457519060-6038-6-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
2016-03-17 17:15 ` Rob Herring
2016-03-09 10:24 ` [PATCH v2 06/18] dt-bindings: Add Oxford Semiconductors to vendor prefixes Neil Armstrong
2016-03-17 17:16 ` Rob Herring
2016-03-09 10:24 ` [PATCH v2 08/18] dt-bindings: Add PLX Technology Reset Controller bindings Neil Armstrong
[not found] ` <1457519060-6038-9-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
2016-03-17 17:18 ` Rob Herring
2016-03-09 10:24 ` [PATCH v2 10/18] dt-bindings: Add PLX Technology OXNAS Standard Clocks bindings Neil Armstrong
2016-03-17 17:19 ` Rob Herring
2016-03-09 10:24 ` [PATCH v2 12/18] dt-bindings: Add PLX Technology OXNAS pinctrl and gpio bindings Neil Armstrong
2016-03-17 17:25 ` Rob Herring
[not found] ` <1457519060-6038-1-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
2016-03-09 10:24 ` [PATCH v2 15/18] arm: boot: dts: Add PLX Technology OX810SE dtsi Neil Armstrong
2016-03-09 10:24 ` [PATCH v2 18/18] arm: boot: dts: Add Western Digital My Book World Edition device tree Neil Armstrong
2016-03-09 10:24 ` [PATCH v2 16/18] dt-bindings: Add OXNAS bindings Neil Armstrong
[not found] ` <1457519060-6038-17-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
2016-03-17 17:27 ` Rob Herring
2016-03-23 8:37 ` Neil Armstrong
2016-03-09 10:24 ` [PATCH v2 17/18] dt-bindings: Add Western Digital to vendor prefixes Neil Armstrong
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