From: Linus Walleij <linus.walleij@linaro.org>
To: Olof Johansson <olof@lixom.net>
Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>,
Alan Tull <atull@altera.com>,
Alexandre Courbot <gnurou@gmail.com>,
"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Dinh Nguyen <dinguyen@altera.com>,
Alan Tull <delicious.quinoa@gmail.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH 1/7] ARM: dts: socfpga: add gpio pieces
Date: Tue, 13 May 2014 10:45:24 +0200 [thread overview]
Message-ID: <CACRpkdZ+OG0FXkgnkdiyhRobSvo+9=ouXc6qes_UCGhitFhTXQ@mail.gmail.com> (raw)
In-Reply-To: <CAOesGMi_0fT4UbfGUp9jkrwYMXgfxC5gmXOBviU9PjAutPdHiw@mail.gmail.com>
On Tue, May 6, 2014 at 12:02 AM, Olof Johansson <olof@lixom.net> wrote:
> ... or is there some underlying reason for having the two-layer
> approach that isn't obvious from this device tree?
There is, as explained by Alan. One coherent memory range with
several individual ports.
Yours,
Linus Walleij
next prev parent reply other threads:[~2014-05-13 8:45 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1395505004-22650-1-git-send-email-bigeasy@linutronix.de>
2014-03-22 16:16 ` [PATCH 1/7] ARM: dts: socfpga: add gpio pieces Sebastian Andrzej Siewior
2014-05-05 22:02 ` Olof Johansson
[not found] ` <CAOesGMi_0fT4UbfGUp9jkrwYMXgfxC5gmXOBviU9PjAutPdHiw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-05-06 15:01 ` Alan Tull
2014-05-13 8:45 ` Linus Walleij [this message]
2014-03-22 16:16 ` [PATCH 2/7] gpio: dwapb: correct gpio-cells in binding document Sebastian Andrzej Siewior
2014-03-25 20:49 ` Linus Walleij
2014-03-25 20:57 ` Sebastian Andrzej Siewior
2014-03-25 21:00 ` Linus Walleij
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