From mboxrd@z Thu Jan 1 00:00:00 1970 From: Linus Walleij Subject: Re: [PATCH 1/7] ARM: dts: socfpga: add gpio pieces Date: Tue, 13 May 2014 10:45:24 +0200 Message-ID: References: <1395505004-22650-1-git-send-email-bigeasy@linutronix.de> <1395505004-22650-2-git-send-email-bigeasy@linutronix.de> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Olof Johansson Cc: Sebastian Andrzej Siewior , Alan Tull , Alexandre Courbot , "linux-gpio@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Dinh Nguyen , Alan Tull , "devicetree@vger.kernel.org" List-Id: devicetree@vger.kernel.org On Tue, May 6, 2014 at 12:02 AM, Olof Johansson wrote: > ... or is there some underlying reason for having the two-layer > approach that isn't obvious from this device tree? There is, as explained by Alan. One coherent memory range with several individual ports. Yours, Linus Walleij