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AJvYcCXYHRTZEeIBFB9A80l2Ow+rBd8uRZ+/JOdG9qpZGCcHWV35MsKA7UdiTt7NKmFX2VJfSq8jkYw4fRwz@vger.kernel.org X-Gm-Message-State: AOJu0YztXk5GuGV2H2Ugg+dvs7vpjugn7oerbUB3JYyQ6h0PYrRD7MWO wbiHHBnkTXQQVdbEl2nH+tnKBwH1L+HVzb57yx5AcDHh4xpKYCJf0tsP2PvYUbu1p6W3ob2F+p4 JlAGq5VLV54Ywhi01PoAbu+VCfifDkEEHyRmwdBkmUw== X-Gm-Gg: ASbGncvWFiQFHONXi73Cfir4xIOz7qdImYo0qAt9sskhPvgMjwCYraxv0Vw7qGZ/HNk 9in1cDe116Rr4+BPHjKUCFdvLthIjnKfhHU0IJV6xYNKzZ4Rc26HJH7pJ8V+3hROzuAtLOUtwv/ ZTzU9Ta1gvxvVN3ooyQe3tN1/DrtjR2UADsezl2/RhIPmm4OVmbotI9B7UMr2dIFGEBrvOWATpZ nIj8l8XowTr3zUgN9w5LUCL8hH5BeB47gjVD4xFek7Cl+58iz4PKxu8dZoQ X-Google-Smtp-Source: AGHT+IGgJO7Zemo+LpoVZasQFrmgPrpk7XQQVTw1/TLYvKF3dmLuG/UrVSSNariPEoGP40bDmIuuuFjLjUnIT++2s6Q= X-Received: by 2002:a05:651c:211c:b0:365:6b40:8656 with SMTP id 38308e7fff4ca-37797948f9bmr5445311fa.35.1760654492708; Thu, 16 Oct 2025 15:41:32 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20251014140451.1009969-1-antonio.borneo@foss.st.com> <20251014140451.1009969-3-antonio.borneo@foss.st.com> <20251014-barbecue-crewman-717fe614daa6@spud> In-Reply-To: From: Linus Walleij Date: Fri, 17 Oct 2025 00:41:21 +0200 X-Gm-Features: AS18NWCfvCVaxN-I2xhCPM2ryQoUWNo2dnNVl4LEycz99TO_NsvVsr2xAwj_RzE Message-ID: Subject: Re: [PATCH v3 02/10] dt-bindings: pincfg-node: Add properties 'skew-delay-{in,out}put' To: Andrew Lunn Cc: Conor Dooley , Antonio Borneo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Christophe Roullier , Fabien Dessenne , Valentin Caron Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, Oct 15, 2025 at 6:37=E2=80=AFPM Andrew Lunn wrote: > > I don't recall the reason for this way of defining things, but one reas= on > > could be that the skew-delay incurred by two inverters is very > > dependent on the production node of the silicon, and can be > > nanoseconds or picoseconds, these days mostly picoseconds. > > Example: Documentation/devicetree/bindings/net/adi,adin.yaml > > > I'm missing the big picture here, and i don't see an example of these > properties being used. However, since you reference an old networking > example, for RGMII delays.... > > adi,rx-internal-delay-ps should be deprecated, we now have the generic > rx-internal-delay-ps. The point about using -ps is however still > valid. > > However, i would not like to see pinctl DT properties used in place of > rx-internal-delay-ps. How the Ethernet MAC driver implements > rx-internal-delay-ps is left open, so calling a pinctl API to set the > skew is fine by me. And if the real use case has nothing to do with > networking, then i don't care. The scope here is to describe skewing the timing of any line connected to a pin, no matter the purpose. Could be an MMC card for example, or something else, but the point is that the control registers are general and inside the SoC perimeter, i.e. around the pins, not necessarily related to any specific hardware block. But I guess it could be used for a line used by some ethernet interface. But the config here happens on the pin controller, so a specific hardware block distinct from e.g. an MMC controller or Ethernet MAC, the latter just have their lines routed through it. The pin controller will handle some pin named "TX", which is just a string, a pin controller does not know what this means, if it is a UART TX or a MAC TX but it can configure the skew delay of the pin named like so. Yours, Linus Walleij