From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D783C388F7 for ; Tue, 10 Nov 2020 14:18:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2D7EE207D3 for ; Tue, 10 Nov 2020 14:18:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="dySosniD" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730099AbgKJOS4 (ORCPT ); Tue, 10 Nov 2020 09:18:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730760AbgKJOSy (ORCPT ); Tue, 10 Nov 2020 09:18:54 -0500 Received: from mail-lf1-x142.google.com (mail-lf1-x142.google.com [IPv6:2a00:1450:4864:20::142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E1D0DC0613D4 for ; Tue, 10 Nov 2020 06:18:51 -0800 (PST) Received: by mail-lf1-x142.google.com with SMTP id u18so17728070lfd.9 for ; Tue, 10 Nov 2020 06:18:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=yEb8SLvwYM6675N1kcLu33g5b43ooDKnUWDg2MuNw70=; b=dySosniDNPpgvWYF4+JGAVaSJLsfzMMHchLwrnUw7r39jGDntjB0KjI86SPwnxMR6L d14V7OlbU1WDRfwoXkx6VPRKNYd+dKojut7EImce3jBAZL4x/MbsJSUO/UzMM8JMKyOe q2KwphZsBP2cGW06PXu0h64z9B6Ldr0uo+jezxWNRu5HFkDXSb9WS3dfHJmk4pkTHmun xAiWGNHwY+DHgl2LMrU9speqjv1MBlOl1y5WbsKUDsN5f8IoPPRIMk5+4j1WxCId9dtG 811Pv4gP2GBQ8Tkdvihd7JqGt89vdyUiN7Pw4TdZUdPmbLgP0WmSqLHG4DF36jlB/XIe c62Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=yEb8SLvwYM6675N1kcLu33g5b43ooDKnUWDg2MuNw70=; b=SOg+XXixNPhPl19ZZLHXFgLeQpGw37U4lbBZzjgGe16GeU3pb1jUFAYhLqCr2SDRP7 06A+E5SGnBwMKyDYhCdxRu6SJnhY7htPcUB7Okn6+Ishdy9Mrs9+XX4/rhMi3sZWbisG XanH7ktqixk5fS952bIsMOXlBZqjm16jXuV3jUTpuLkYuR0bbeVEVFJloNDth42SvzCY NeIf5p5dNyv1z4ooRqG8pDoB8ersQDHluahG8ieRuksaAa8wqzrFuOytJ0ltGqNh/IfX he86ERXndq1EyneXY78IzmB+DFToAHyLx14ctkgVra1nQyD86IAo/LX9GjjzmEKC3lnH YT6g== X-Gm-Message-State: AOAM533fp+k2hYjWT2Se688BYpYEBv3Qov1GSgio1dDmccZa98SLgCZ1 0eGcOSkbzHfek6cxPjWIPhrC3tIUhiPaWW88JNLoqw== X-Google-Smtp-Source: ABdhPJx8DR3A9HZXVyV5Hw/ZIpPtbFQchtKdOZgI87BTIuRS9xLwWyIYq34Y5zWUwvd/nYChAFW4q26/YE5DXMVzvfw= X-Received: by 2002:a19:ca05:: with SMTP id a5mr4558685lfg.571.1605017930249; Tue, 10 Nov 2020 06:18:50 -0800 (PST) MIME-Version: 1.0 References: <20201105120410.18305-1-srinivas.kandagatla@linaro.org> <20201105120410.18305-2-srinivas.kandagatla@linaro.org> In-Reply-To: From: Linus Walleij Date: Tue, 10 Nov 2020 15:18:39 +0100 Message-ID: Subject: Re: [PATCH v2 1/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver To: Srinivas Kandagatla Cc: Bjorn Andersson , Rob Herring , Andy Gross , MSM , "open list:GPIO SUBSYSTEM" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, Nov 6, 2020 at 12:08 PM Srinivas Kandagatla wrote: > Some more detail of wiring of this additional pin-controller IP: > > This IP is an additional pinctrl block on top the existing SoC TLMM > pin-controller (Audio) pins. > > The hw setup looks like: > > TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13] > > However SoC TLMM pin-controller can only be touched for use of those > pins in GPIO mode and non gpio mode is completely handled by the LPASS > LPI pinctrl block. Apart from this slew rate is also available in this > block for certain pins which are connected to SLIMbus or SoundWire Bus. OK put this in the commit message, good to know! I gues the pins are not quite "GPIO" at this point, instead they are turned into LPASS pins? > Normally we would not expect these pins to be touched by SoC TLMM > pin-controller as these pins are used for audio usecase and the control > is always with LPASS LPI controller. There are additional bits to > configure/enforce this in SoC TLMM block! If you start to use IRQs they might become hierarchical WRT the TLMM. But no IRQ support yet, so... Yours, Linus Walleij