From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F31AC433DB for ; Tue, 2 Mar 2021 20:31:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0925064F25 for ; Tue, 2 Mar 2021 20:31:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1446160AbhCBU1h (ORCPT ); Tue, 2 Mar 2021 15:27:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238703AbhCBP2W (ORCPT ); Tue, 2 Mar 2021 10:28:22 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6BD71C0611BE for ; Tue, 2 Mar 2021 07:23:49 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id m22so31890052lfg.5 for ; Tue, 02 Mar 2021 07:23:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=phGkBVfIBc9N8/MYw3IsLowc0jNOtyQmeOezRPC5r6A=; b=IxEHOA/EeqJE9XesCg+nCfa3QJs4ZoTXMJRRwtoaO1dsS8/djz+UWJbAs59nUIy3FV K2RJk37iYNtFVVMwae8n2KqT6KXLsaMz+DupUwBbV3X/QoDQ3QmSZlw3bqnfXr7x0M9+ 6Bh00Lr5x3pTcsF0kX9ES2A3AGs/6hVNMJgkt9DHcPtr2p6TBqiDz3+Q14EH3dVEQv15 PrI8M8O/MX6KRxLXecPHArez80P4gQQyHbwfXn1ItS3rQb840an7hPuiGWs44bUMI0qx 1KWBY+Jpl9RKhWAFucv/VKzCkBEdA3ykrcitpsdOQaBpyVqG7G7SMRpyjKYYMgDZ0Xxw eXxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=phGkBVfIBc9N8/MYw3IsLowc0jNOtyQmeOezRPC5r6A=; b=ATlelg5f1Z8NOrUzgab+HWWCuqxFxa0oyKnugBHXWcjjOh5bnukCc+s49hqk81na3X hcV1ubYng97XVnzIAVLvo/DVkoa/ivDKBk1EGJm442GSH3E+RIqgrizo87bIiYaxKJJT 8aPruVNWc3Wc2AHyc+rNbyZN/14strnZGZXIetCEpFU1oFZhBrX9SyM4im7kfVqMsN4Q xqZHFJkk1HjTdaq2zdru9jIkyYbIGg9BMqQmqtcEJ6c0bt4+2Fz4zQls2VfTaA5uJ6fE fMZjdsZExkwYlcYnqS58FehAzm7AiwflmFjY6kH5GUxuQ41KmurL2vczrw9o0yCBQPAV rZtw== X-Gm-Message-State: AOAM533YID2Zyo+064qGVXOQDV7p4H9sZsed0yvzxmI0X3Y4zlS/xjcC ofWc4ZIfF85U6FP92Jmi9klhWdNGCoM0VXPQlkKknw== X-Google-Smtp-Source: ABdhPJyFEssv4TZ20RIixukIPx4G+ICtagjbJAX9g02ycgsPC8yvfaoZNRA54LDHGtijXLpyZkxVrklKXkjozmYype0= X-Received: by 2002:a05:6512:547:: with SMTP id h7mr12960505lfl.529.1614698627904; Tue, 02 Mar 2021 07:23:47 -0800 (PST) MIME-Version: 1.0 References: <20210225164216.21124-1-noltari@gmail.com> <20210225164216.21124-2-noltari@gmail.com> In-Reply-To: From: Linus Walleij Date: Tue, 2 Mar 2021 16:23:36 +0100 Message-ID: Subject: Re: [PATCH 01/12] Documentation: add BCM6328 pincontroller binding documentation To: =?UTF-8?B?w4FsdmFybyBGZXJuw6FuZGV6IFJvamFz?= Cc: Florian Fainelli , Rob Herring , Jonas Gorski , Necip Fazil Yildiran , "open list:GPIO SUBSYSTEM" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, Mar 2, 2021 at 3:57 PM Linus Walleij wro= te: > On Thu, Feb 25, 2021 at 5:42 PM =C3=81lvaro Fern=C3=A1ndez Rojas > wrote: > > > Add binding documentation for the pincontrol core found in BCM6328 SoCs= . > > > > Signed-off-by: =C3=81lvaro Fern=C3=A1ndez Rojas > > Signed-off-by: Jonas Gorski > (...) > > + interrupts-extended: > > + description: > > + One interrupt per each of the 4 GPIO ports supported by the cont= roller, > > + sorted by port number ascending order. > > + minItems: 4 > > + maxItems: 4 > > I don't know if this is advisable, there are different ways > of specifying interrupts so this may become ambiguous, > I think Rob will know how/if to do this though. After reading the code I conclude this gpiochip is hierarchical so this sho= uld just be dropped, and we only need interrupt-parent assigned. The driver will know the hardware offsets between the interrupt parent and the GPIO block, this is generally the case for hierarchical interrupt controllers. Yours, Linus Walleij