From mboxrd@z Thu Jan 1 00:00:00 1970 From: Linus Walleij Subject: Re: [PATCH v9 01/22] pinctrl: tegra: Fix write barrier placement in pmx_writel Date: Mon, 19 Aug 2019 00:20:01 +0200 Message-ID: References: <1565984527-5272-1-git-send-email-skomatineni@nvidia.com> <1565984527-5272-2-git-send-email-skomatineni@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: In-Reply-To: <1565984527-5272-2-git-send-email-skomatineni@nvidia.com> Sender: linux-kernel-owner@vger.kernel.org To: Sowjanya Komatineni Cc: "thierry.reding@gmail.com" , Jon Hunter , Thomas Gleixner , Jason Cooper , Marc Zyngier , Stefan Agner , Mark Rutland , Peter De Schrijver , Prashant Gaikwad , Stephen Boyd , linux-clk , "open list:GPIO SUBSYSTEM" , jckuo@nvidia.com, Joseph Lo , talho@nvidia.com, linux-tegra@vger.kernel.org, "linux-kernel@vger.kernel.org" , Mikko Perttunen , spatra@nvidia.com, Rob Herring , Dmitry Osipenko List-Id: devicetree@vger.kernel.org On Fri, Aug 16, 2019 at 9:42 PM Sowjanya Komatineni wrote: > > pmx_writel uses writel which inserts write barrier before the > register write. > > This patch has fix to replace writel with writel_relaxed followed > by a readback and memory barrier to ensure write operation is > completed for successful pinctrl change. > > Acked-by: Thierry Reding > Reviewed-by: Dmitry Osipenko > Signed-off-by: Sowjanya Komatineni Took out the previous patches and applied this instead. Yours, Linus Walleij