Re: [PATCH 2/2] pinctrl: Add Pistachio SoC pin control driver

[Linus Walleij <linus.walleij@linaro.org>]

On Tue, Mar 17, 2015 at 5:56 PM, Andrew Bresticker
<abrestic@chromium.org> wrote:
[Me]
>> Sorry if I don't really know how things work now... :(
>> It seems like a logical way to me.
(...)
> 4) The ->set_mux() op must set the proper function for the pin.
> 5) The ->set_mux() op must also disable the GPIO function for the pin.
> To disable the GPIO function, the pinctrl driver must map the pin to a
> GPIO bank/offset and disable the GPIO via the GPIO bank's GPIO_EN
> register.

That sounds like the"GPIO" registers are actually involved in any
muxing usecase, meaning there is not really a clean split between
the pinctrl and GPIO hardware, the case I refer to as "GPIO mode
pitfalls" in Documentation/pinctrl.txt.

In such cases both halves of the driver(s) need to be aware of
the other, and that is what you seem to be wanting to achieve.

So I was wrong in thinking the GPIO device could be a separate
subdevice, the two parts are too dependent on each other.
So keep a single probe() function and let the two driver halves
poke into each others' registers.

Sorry for the fuzz...

Yours,
Linus Walleij