Re: [PATCH 1/2] dt-bindings: gpio: lpc18xx: describe interrupt controllers of GPIO controller

[Linus Walleij <linus.walleij@linaro.org>]

On Wed, Nov 28, 2018 at 11:48 PM Vladimir Zapolskiy <vz@mleia.com> wrote:

> From LPC18xx and LPC43xx User Manuals the GPIO controller consists of
> the following weakly connected blocks:
> * GPIO pin interrupt block at 0x40087000,
> * GPIO GROUP0 interrupt block at 0x40088000,
> * GPIO GROUP1 interrupt block at 0x40089000,
> * GPIO port block at 0x400F4000.
>
> While all 4 sub-controller blocks have their own I/O addresses, moreover
> all 3 interrupt blocks are APB0 peripherals and high-speed GPIO block is
> an AHB slave, according to the hardware manual interrupt controllers and
> GPIO controller block are seen as a single device, all 4 sub-controllers
> have the shared reset signal RGU #28 and the same shared clock to access
> registers CLK_Mx_GPIO on CCU1.
>
> The change adds descriptions of the currently missing interrupt controller
> blocks found on GPIO controller, new added properties are 'reg-names',
> 'resets', 'interrupt-controller' and '#interrupt-cells', also the example
> is updated to reflect the changes in device tree binding description.
>
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>

That is some seriously Frankenstein hardware.

But I see no problem with the way you are dealing with it,
it seems pretty much to the point.

So: patch applied.

Yours,
Linus Walleij