From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFBFE22370A for ; Wed, 10 Dec 2025 23:45:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765410343; cv=none; b=FbrTCDLdLkOhMIPDFVc55q7/KqzOAHyUO7qov79jAt3onbj7wAkk+YZUw6kIMpcDiqr7znZ5BVPdJd6E6uFwRxOqnakcL8ilm1BuUxRVevEy+FvBfUsRQhH8zEZEGTDYV+QMqkHCNib6DlZD6FO0wbNqVE2MuRRIFy41yCldOFM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765410343; c=relaxed/simple; bh=HF42HWiCI324GsDSWGrNrq+cMfLqL2KF13nwFnUL2Vo=; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject: To:Cc:Content-Type; b=m3O46Fuy6GQ7orK256vVWXmtKuAtiq9cz5WPPetWC0loYDlGCBWa9TlfMMCbPvXDBTZXYSr0LnCejCDDHiBY4ByLJKOTelNmj1Nsip7Q/F4aKDHb5RJ6QOgb9Na6LxlGeIaz6NoC8nRdA8qsp+Nl/glFWrYoN3SLH25yHWrE/2E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ezM1XI72; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ezM1XI72" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8ED0FC2BC86 for ; Wed, 10 Dec 2025 23:45:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1765410343; bh=HF42HWiCI324GsDSWGrNrq+cMfLqL2KF13nwFnUL2Vo=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=ezM1XI72XFaFJ1c6/EyFn30UIUaFd6K2HKxti8lVFhOUpWOM8PXIWf2FNe7TDYyOz hSVHrsq/zNh47Uv74nsVnarb/sj+LBcVHxbHU1GMG15nbU8pNEiMDiuYqEf/T/8SSx V8MnhQ29zbSUApNYGwApjpfA6wp70lDGSp3FTTggqGn6ulteFu0pq8T3kXTUs9STZi KAXRgm8Voe+AMz/RTUygR+wtS/mJJWLh/RauswIBcBWFFmQxZdUt8zmWsx0Ly1viBg OqeuZ8NOZUDYO/Wo81I9WbnRMgqnE3sfCOpxHsySOCxcVM9tx36r+w2Uhi9yAdk9v4 IaLhNmWM5CaMg== Received: by mail-yw1-f170.google.com with SMTP id 00721157ae682-78c38149f9fso3557407b3.2 for ; Wed, 10 Dec 2025 15:45:43 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCX5qVzWrSpSwjwFoDjtJM9jvv57HA4Bb6SXnQMGtx+xnBMgb8yKWMXdQ/q4wSZAYShj01qvuezHfrVr@vger.kernel.org X-Gm-Message-State: AOJu0Yyh1VxXc6gXKYyRS/i1PkN2Yp4TLMsqbIP9Y12EFOZ7JO+evx0N ymAUFYdLIQKyRbYEfy80gFn2b0i311pbKODj7OlBzti9N/eIUfqVPZP0pbORwdlcDZbl/2uAOa8 YF9ypIZxCEwZE140RB3Y8JU2qowYfk6w= X-Google-Smtp-Source: AGHT+IHu6mB/moS2krcEaW8l5HpAQusE8zC+ia9FhxigsEkptctsTlXdWxt92NBjJgrpbtNpUfMMfrsXr83s8/ptEVE= X-Received: by 2002:a05:690c:9a0e:b0:786:68da:26d6 with SMTP id 00721157ae682-78c95a30284mr35149207b3.2.1765410342908; Wed, 10 Dec 2025 15:45:42 -0800 (PST) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20251205150234.2958140-1-cosmin-gabriel.tanislav.xa@renesas.com> <20251205150234.2958140-5-cosmin-gabriel.tanislav.xa@renesas.com> In-Reply-To: <20251205150234.2958140-5-cosmin-gabriel.tanislav.xa@renesas.com> From: Linus Walleij Date: Thu, 11 Dec 2025 00:45:32 +0100 X-Gmail-Original-Message-ID: X-Gm-Features: AQt7F2orPEAyNX9tS0S-VYCOLiiLQfh-OmMwhQoomLnhwzgJukPY3XEauYlkSU0 Message-ID: Subject: Re: [PATCH v2 4/8] pinctrl: renesas: rzt2h: add GPIO IRQ chip to handle interrupts To: Cosmin Tanislav Cc: Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Lad Prabhakar , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Dec 5, 2025 at 4:03=E2=80=AFPM Cosmin Tanislav wrote: > The Renesas RZ/T2H (R9A09G077) and Renesas RZ/N2H (R9A09G087) SoCs have > IRQ-capable pins handled by the ICU, which forwards them to the GIC. > > The ICU supports 16 IRQ lines, the pins map to these lines arbitrarily, > and the mapping is not configurable. > > Add a GPIO IRQ chip to the pin controller that can be used to configure > these pins as IRQ lines. > > The pin controller places the requested pins into IRQ function, > disabling GPIO mode. A hierarchical IRQ domain is used to forward other > functionality to the parent IRQ domain, the ICU. The ICU does level > translation and then forwards other functionality to the GIC. > > Wakeup capability is implemented by placing the entire pin controller on > the wakeup path if any pins are requested to be wakeup-capable. > > Signed-off-by: Cosmin Tanislav Reviewed-by: Linus Walleij Yours, Linus Walleij