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[209.85.128.48]) by smtp.gmail.com with ESMTPSA id x18-20020a170906805200b0097073f1ed84sm7247353ejw.4.2023.08.30.07.30.53 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Aug 2023 07:30:53 -0700 (PDT) Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-3fe2d620d17so97065e9.0 for ; Wed, 30 Aug 2023 07:30:53 -0700 (PDT) X-Received: by 2002:a05:600c:4f93:b0:3f4:fb7:48d4 with SMTP id n19-20020a05600c4f9300b003f40fb748d4mr325936wmq.3.1693405853267; Wed, 30 Aug 2023 07:30:53 -0700 (PDT) MIME-Version: 1.0 References: <20230830-fp5-initial-v1-0-5a954519bbad@fairphone.com> <20230830-fp5-initial-v1-2-5a954519bbad@fairphone.com> In-Reply-To: <20230830-fp5-initial-v1-2-5a954519bbad@fairphone.com> From: Doug Anderson Date: Wed, 30 Aug 2023 07:30:41 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 02/11] nvmem: qfprom: Mark core clk as optional To: Luca Weiss Cc: cros-qcom-dts-watchers@chromium.org, Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Linus Walleij , "Rafael J. Wysocki" , Viresh Kumar , ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi, On Wed, Aug 30, 2023 at 2:58=E2=80=AFAM Luca Weiss wrote: > > On some platforms like sc7280 on non-ChromeOS devices the core clock > cannot be touched by Linux so we cannot provide it. Mark it as optional > as accessing qfprom works without it. > > Signed-off-by: Luca Weiss > --- > drivers/nvmem/qfprom.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Are you actually testing burning fuses from the OS, or are you just using the nvmem in "read-only" mode? From comments in the bindings, if you're trying to burn the fuses then the clock is required. If things are in read-only mode then the clock isn't required. When I compare to the driver, it seems like the driver assumes that if more than one memory region is provided then you must be supporting burning fuses. The bindings agree that having 4 memory regions specified means that the nvmem supports burning and 1 memory region specified means read-only. The extra 3 memory regions in the nvmem are all about fuse burning, I believe. So maybe the right fix here is to just change your dts to specify one memory region? -Doug