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AJvYcCUjKqzfvUx28brBOafDs5lME6eQapQS+s3DEG/enJOYsDlzGBnglcFnE8Fw8Pr6uHohB8jLtigZTYj2X7pIFOzVPDr6XqrwW3bWMA== X-Gm-Message-State: AOJu0YyJ/Sv0QpM8a0U7GWBVzDB5nS01wnB2M8PgxCDXCcRCARgoac2E 9phScXjHbZaDlaXrqLIaK/vCWtosyWwK/QAlVH/E13apf3fXunVGI86SKxaeIdec7pH1Rnl+LZ8 /vms6jfPERajTjk2QgA23n/5L8C7k4uY59E9n2w== X-Google-Smtp-Source: AGHT+IGdAJXHt7mAsVZuzt9JgE7vdWoLagtGQT3T15A+kBPHpQZl6zuXKVT8ycszrHB5VvpVeZdYSex6pwkAq/Bp7sg= X-Received: by 2002:a4a:aecb:0:b0:5ac:9efc:3b02 with SMTP id v11-20020a4aaecb000000b005ac9efc3b02mr5501112oon.8.1713268621486; Tue, 16 Apr 2024 04:57:01 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240404122559.898930-1-peter.griffin@linaro.org> <20240404122559.898930-6-peter.griffin@linaro.org> <391a874522a4141b4bc7f0314a9e50d27142123a.camel@linaro.org> In-Reply-To: <391a874522a4141b4bc7f0314a9e50d27142123a.camel@linaro.org> From: Peter Griffin Date: Tue, 16 Apr 2024 12:56:50 +0100 Message-ID: Subject: Re: [PATCH 05/17] arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller To: =?UTF-8?Q?Andr=C3=A9_Draszik?= Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, kishon@kernel.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, jejb@linux.ibm.com, martin.petersen@oracle.com, chanho61.park@samsung.com, ebiggers@kernel.org, linux-scsi@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tudor.ambarus@linaro.org, saravanak@google.com, willmcvicker@google.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Andr=C3=A9, Thanks for the review. On Fri, 5 Apr 2024 at 08:38, Andr=C3=A9 Draszik = wrote: > > On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote: > > Enable the cmu_hsi2 clock management unit. It feeds some of > > the high speed interfaces such as PCIe and UFS. > > > > Signed-off-by: Peter Griffin > > --- > > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++ > > 1 file changed, 12 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/= boot/dts/exynos/google/gs101.dtsi > > index eddb6b326fde..38ac4fb1397e 100644 > > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi > > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > > @@ -1253,6 +1253,18 @@ pinctrl_hsi1: pinctrl@11840000 { > > interrupts =3D ; > > }; > > > > + cmu_hsi2: clock-controller@14400000 { > > + compatible =3D "google,gs101-cmu-hsi2"; > > + reg =3D <0x14400000 0x4000>; > > + #clock-cells =3D <1>; > > + clocks =3D <&ext_24_5m>, > > + <&cmu_top CLK_DOUT_CMU_HSI2_BUS>, > > + <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>, > > + <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>, > > + <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>; > > + clock-names =3D "oscclk", "bus", "pcie", "ufs_emb= d", "mmc_card"; > > + }; > > This doesn't build because you didn't add the clock ids in the binding pa= tch. These clock IDs are for cmu_top, not cmu_hsi2. They were added as part of the initial gs101/Oriole upstream support series in the following commit commit 0a910f1606384a5886a045e36b1fc80a7fa6706b Author: Peter Griffin Date: Sat Dec 9 23:30:48 2023 +0000 dt-bindings: clock: Add Google gs101 clock management unit bindings Provide dt-schema documentation for Google gs101 SoC clock controller. Currently this adds support for cmu_top, cmu_misc and cmu_apm. Reviewed-by: Sam Protsenko Signed-off-by: Peter Griffin Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20231209233106.147416-3-peter.griffin@l= inaro.org Signed-off-by: Krzysztof Kozlowski regards, Peter