From: Stephen Boyd <swboyd@chromium.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Rajesh Patil <rajpat@codeaurora.org>,
Rob Herring <robh+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, rnayak@codeaurora.org,
saiprakash.ranjan@codeaurora.org, msavaliy@qti.qualcomm.com,
skakit@codeaurora.org, Roja Rani Yarubandi <rojay@codeaurora.org>
Subject: Re: [PATCH V6 1/7] arm64: dts: sc7280: Add QSPI node
Date: Thu, 26 Aug 2021 18:02:17 +0000 [thread overview]
Message-ID: <CAE-0n50-9df1riEwcbbS9Dxd5WhKFBKqXAHu-bkwdP4z1NKTWA@mail.gmail.com> (raw)
In-Reply-To: <1629983731-10595-2-git-send-email-rajpat@codeaurora.org>
Can you please Cc folks who have reviewed prior series when you send
again?
Quoting Rajesh Patil (2021-08-26 06:15:25)
> From: Roja Rani Yarubandi <rojay@codeaurora.org>
>
> Add QSPI DT node and qspi_opp_table for SC7280 SoC.
Might be worth adding here that we put the opp table in / because SPI
nodes assume any child node is a spi device and so we can't put the
table underneath the spi controller.
>
> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 62 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 62 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 53a21d0..f8dd5ff 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1318,6 +1337,24 @@
> };
> };
>
> + qspi: spi@88dc000 {
> + compatible = "qcom,qspi-v1";
> + reg = <0 0x088dc000 0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
> + <&gcc GCC_QSPI_CORE_CLK>;
> + clock-names = "iface", "core";
> + interconnects = <&gem_noc MASTER_APPSS_PROC 0
> + &cnoc2 SLAVE_QSPI_0 0>;
> + interconnect-names = "qspi-config";
> + power-domains = <&rpmhpd SC7280_CX>;
> + operating-points-v2 = <&qspi_opp_table>;
> + status = "disabled";
> +
Nitpick: Drop newline above.
> + };
> +
> dc_noc: interconnect@90e0000 {
> reg = <0 0x090e0000 0 0x5080>;
> compatible = "qcom,sc7280-dc-noc";
next prev parent reply other threads:[~2021-08-26 18:02 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-26 13:15 [PATCH V6 0/7] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
2021-08-26 13:15 ` [PATCH V6 1/7] arm64: dts: sc7280: Add QSPI node Rajesh Patil
2021-08-26 18:02 ` Stephen Boyd [this message]
2021-08-31 15:29 ` rajpat
2021-08-26 13:15 ` [PATCH V6 2/7] arm64: dts: sc7280: Configure SPI-NOR FLASH for sc7280-idp Rajesh Patil
2021-08-26 18:03 ` Stephen Boyd
2021-08-26 13:15 ` [PATCH V6 3/7] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Rajesh Patil
2021-08-26 18:06 ` Stephen Boyd
2021-08-31 15:28 ` rajpat
2021-08-26 20:08 ` Matthias Kaehlcke
2021-08-26 13:15 ` [PATCH V6 4/7] arm64: dts: sc7280: Update QUPv3 UART5 DT node Rajesh Patil
2021-08-26 21:01 ` Matthias Kaehlcke
2021-08-31 15:27 ` rajpat
2021-08-26 13:15 ` [PATCH V6 5/7] arm64: dts: sc7280: Configure uart7 to support bluetooth on sc7280-idp Rajesh Patil
2021-08-26 13:15 ` [PATCH V6 6/7] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes Rajesh Patil
2021-08-26 18:11 ` Stephen Boyd
2021-08-31 15:28 ` rajpat
2021-09-01 5:04 ` Stephen Boyd
2021-08-26 13:15 ` [PATCH V6 7/7] arm64: dts: sc7280: Add aliases for I2C and SPI Rajesh Patil
2021-08-26 18:12 ` Stephen Boyd
2021-08-31 15:29 ` rajpat
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