From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9027C19F28 for ; Wed, 27 Jul 2022 01:22:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231690AbiG0BWm (ORCPT ); Tue, 26 Jul 2022 21:22:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240094AbiG0BWl (ORCPT ); Tue, 26 Jul 2022 21:22:41 -0400 Received: from mail-ot1-x32e.google.com (mail-ot1-x32e.google.com [IPv6:2607:f8b0:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 188953A49C for ; Tue, 26 Jul 2022 18:22:40 -0700 (PDT) Received: by mail-ot1-x32e.google.com with SMTP id w6-20020a056830410600b0061c99652493so12000361ott.8 for ; Tue, 26 Jul 2022 18:22:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:in-reply-to:references:from:user-agent:date:message-id :subject:to:cc; bh=dzYkFnzKNRLeXUsCkZgu16teiRoh5GfDTn6fhQts7oo=; b=TVdxEej7zvly6wv5TNAXpc5tA5MBNvX/DGGHGbV4/K+2QCoxi/KDJZLcLP7j315seA o5AtXxTy0KkAG4B/NtMBT1I03GAVm0nnfJxWHJy4eT64K9Bmq2PeeOUAdHCdMwQb/vrE efhTMKzgE3SLIMilT/E9yb41+7Fg7c84GhWU4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:in-reply-to:references:from :user-agent:date:message-id:subject:to:cc; bh=dzYkFnzKNRLeXUsCkZgu16teiRoh5GfDTn6fhQts7oo=; b=Wb8x8uSnXFjI2xCDOJ4iXkGgIhrG6UqURAlMJoDDvZkx73EpwemwadekUS2P1D/I7G oJ08FjAq8niMS8ptWy8RHYw0WSQsbyKgdh9V5cWqDqUtjq8fCYntfQLQ9UnLoVyv/1iO AmP6pgIzcCR/HAChXGK7j7pS53wDYznrg2XDhPLjdI1yJZ70qwAr1/dl3n8YX5yjXQWA +109ozdFr6yQSkIVNvlvcPkvHN9J78YrfkYhaNZ3bmuGOc801DgYA5veWqzmoyiD2KxG h9vo8/0lTuXZF0gv1bxXX+HI7prQptjdTbmlLGXKMWKXxS1zJdTVuCKpPa1Nvv87ekxe nfkw== X-Gm-Message-State: AJIora9YZpQ3Kt3h2XIEb3cLjUu1FKSxbBCryvAcWJvzNbnrC+keoRbI dnKKnXeSeGY92N+I0/e7cKFD5Ep5YZqmA3qkakluQA== X-Google-Smtp-Source: AGRyM1sUN8naA9fnEOzbQgvRY9ky+jL0upLCp5I5rFs9OptUN1BFlt0Rf5afSFJtK4EPV+OGI/OwMBRlTGCFxFfuUCk= X-Received: by 2002:a05:6830:1d88:b0:61c:8b2a:22b0 with SMTP id y8-20020a0568301d8800b0061c8b2a22b0mr7833793oti.3.1658884959405; Tue, 26 Jul 2022 18:22:39 -0700 (PDT) Received: from 753933720722 named unknown by gmailapi.google.com with HTTPREST; Tue, 26 Jul 2022 20:22:38 -0500 MIME-Version: 1.0 In-Reply-To: <1658316144-16520-3-git-send-email-quic_c_skakit@quicinc.com> References: <1658316144-16520-1-git-send-email-quic_c_skakit@quicinc.com> <1658316144-16520-3-git-send-email-quic_c_skakit@quicinc.com> From: Stephen Boyd User-Agent: alot/0.10 Date: Tue, 26 Jul 2022 20:22:38 -0500 Message-ID: Subject: Re: [PATCH V3 2/2] arm64: dts: qcom: sc7280: Update lpassaudio clock controller for resets To: Bjorn Andersson , Rob Herring , Satya Priya Cc: Douglas Anderson , Andy Gross , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_tdas@quicinc.com Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Quoting Satya Priya (2022-07-20 04:22:24) > From: Taniya Das > > The lpass audio supports TX/RX/WSA block resets. Also to keep > consistency update lpasscore to lpass_core. Consistency with what? > > Fixes: 9499240d15f2 ("arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers") > Signed-off-by: Taniya Das > Signed-off-by: Satya Priya > --- > Changes since v3: > - Remove the status="disabled" from lpasscc node. > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 71735bb..c641f0b 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -2184,6 +2184,7 @@ > power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; > #clock-cells = <1>; > #power-domain-cells = <1>; > + #reset-cells = <1>; Is there a binding update for qcom,sc7280-lpassaudiocc? > }; > > lpass_aon: clock-controller@3380000 { > @@ -2191,13 +2192,13 @@ > reg = <0 0x03380000 0 0x30000>; > clocks = <&rpmhcc RPMH_CXO_CLK>, > <&rpmhcc RPMH_CXO_CLK_A>, > - <&lpasscore LPASS_CORE_CC_CORE_CLK>; > + <&lpass_core LPASS_CORE_CC_CORE_CLK>; Is this really necessary? > clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; > #clock-cells = <1>; > #power-domain-cells = <1>; > }; > > - lpasscore: clock-controller@3900000 { > + lpass_core: clock-controller@3900000 { Is this really necessary? > compatible = "qcom,sc7280-lpasscorecc"; > reg = <0 0x03900000 0 0x50000>; > clocks = <&rpmhcc RPMH_CXO_CLK>;