From mboxrd@z Thu Jan 1 00:00:00 1970 From: Evan Green Subject: Re: [PATCH v6 01/22] dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI Date: Tue, 19 Feb 2019 15:28:54 -0800 Message-ID: References: <1550394300-17420-1-git-send-email-yong.wu@mediatek.com> <1550394300-17420-2-git-send-email-yong.wu@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: In-Reply-To: <1550394300-17420-2-git-send-email-yong.wu@mediatek.com> Sender: linux-kernel-owner@vger.kernel.org To: Yong Wu Cc: Joerg Roedel , Matthias Brugger , Robin Murphy , Rob Herring , Tomasz Figa , Will Deacon , linux-mediatek@lists.infradead.org, srv_heupstream@mediatek.com, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, yingjoe.chen@mediatek.com, youlin.pei@mediatek.com, Nicolas Boichat , anan.sun@mediatek.com, Matthias Kaehlcke List-Id: devicetree@vger.kernel.org On Sun, Feb 17, 2019 at 1:06 AM Yong Wu wrote: > > This patch adds decriptions for mt8183 IOMMU and SMI. > > mt8183 has only one M4U like mt8173 and is also MTK IOMMU gen2 which > uses ARM Short-Descriptor translation table format. > > The mt8183 M4U-SMI HW diagram is as below: > > EMI > | > M4U > | > ---------- > | | > gals0-rx gals1-rx > | | > | | > gals0-tx gals1-tx > | | > ------------ > SMI Common > ------------ > | > +-----+-----+--------+-----+-----+-------+-------+ > | | | | | | | | > | | gals-rx gals-rx | gals-rx gals-rx gals-rx > | | | | | | | | > | | | | | | | | > | | gals-tx gals-tx | gals-tx gals-tx gals-tx > | | | | | | | | > larb0 larb1 IPU0 IPU1 larb4 larb5 larb6 CCU > disp vdec img cam venc img cam > > All the connections are HW fixed, SW can NOT adjust it. > > Compared with mt8173, we add a GALS(Global Async Local Sync) module > between SMI-common and M4U, and additional GALS between larb2/3/5/6 > and SMI-common. GALS can help synchronize for the modules in different > clock frequency, it can be seen as a "asynchronous fifo". > > GALS can only help transfer the command/data while it doesn't have > the configuring register, thus it has the special "smi" clock and it > doesn't have the "apb" clock. From the diagram above, we add "gals0" > and "gals1" clocks for smi-common and add a "gals" clock for smi-larb. > > From the diagram above, IPU0/IPU1(Image Processor Unit) and CCU(Camera > Control Unit) is connected with smi-common directly, we can take them > as "larb2", "larb3" and "larb7", and their register spaces are > different with the normal larb. > > Signed-off-by: Yong Wu Reviewed-by: Evan Green