From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oa0-f48.google.com ([209.85.219.48]:60048 "EHLO mail-oa0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756882Ab3HGRFS (ORCPT ); Wed, 7 Aug 2013 13:05:18 -0400 Received: by mail-oa0-f48.google.com with SMTP id o17so3942219oag.35 for ; Wed, 07 Aug 2013 10:05:15 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <002501ce9324$8066f5a0$8134e0e0$@samsung.com> References: <002501ce9324$8066f5a0$8134e0e0$@samsung.com> From: Bjorn Helgaas Date: Wed, 7 Aug 2013 11:04:54 -0600 Message-ID: Subject: Re: [PATCH V5] pci: exynos: split into two parts such as Synopsys part and Exynos part Content-Type: text/plain; charset=ISO-8859-1 Sender: devicetree-owner@vger.kernel.org To: Jingoo Han Cc: "linux-pci@vger.kernel.org" , linux-samsung-soc@vger.kernel.org, Kukjin Kim , Pratyush Anand , Mohit KUMAR , Arnd Bergmann , Sean Cross , Kishon Vijay Abraham I , Thierry Reding , SRIKANTH TUMKUR SHIVANAND , "linux-kernel@vger.kernel.org" , devicetree@vger.kernel.org List-ID: On Tue, Aug 6, 2013 at 10:13 PM, Jingoo Han wrote: > On Wednesday, July 31, 2013 5:14 PM, Jingoo Han wrote: >> Exynos PCIe IP consists of Synopsys specific part and Exynos >> specific part. Only core block is a Synopsys designware part; >> other parts are Exynos specific. >> Also, the Synopsys designware part can be shared with other >> platforms; thus, it can be split two parts such as Synopsys >> designware part and Exynos specific part. >> >> Signed-off-by: Jingoo Han >> Cc: Pratyush Anand >> Cc: Mohit KUMAR > > Hi Bjorn Helgaas, > > There is no comment for last 2 weeks. > Will you accept this patch? I don't have any problem with this, since it's really arch code. Do you want me to merge it, or do you have a standard path for merging Exynos and/or Designware changes? Bjorn In case you need it: Acked-by: Bjorn Helgaas >> --- >> Changes since v4: >> - fixed section mismatch warnings >> - fixed sparse warnings >> >> .../devicetree/bindings/pci/designware-pcie.txt | 3 + >> arch/arm/boot/dts/exynos5440.dtsi | 2 + >> drivers/pci/host/Makefile | 3 +- >> drivers/pci/host/pci-exynos.c | 530 ++++++++++ >> drivers/pci/host/pcie-designware.c | 1011 ++++++-------------- >> drivers/pci/host/pcie-designware.h | 65 ++ >> 6 files changed, 874 insertions(+), 740 deletions(-) >> create mode 100644 drivers/pci/host/pci-exynos.c >> create mode 100644 drivers/pci/host/pcie-designware.h > >