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From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: Hanjie Lin <hanjie.lin@amlogic.com>
Cc: Rob Herring <robh@kernel.org>,
	Victor Wan <victor.wan@amlogic.com>,
	Jianxin Pan <jianxin.pan@amlogic.com>,
	Neil Armstrong <narmstrong@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Kevin Hilman <khilman@baylibre.com>,
	Michael Turquette <mturquette@baylibre.com>,
	linux-usb@vger.kernel.org, Yue Wang <yue.wang@amlogic.com>,
	Qiufang Dai <qiufang.dai@amlogic.com>,
	devicetree@vger.kernel.org, Liang Yang <liang.yang@amlogic.com>,
	Jian Hu <jian.hu@amlogic.com>,
	Xingyu Chen <xingyu.chen@amlogic.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Carlo Caione <carlo@caione.org>,
	linux-amlogic@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	Jerome Brunet <jbrunet@baylibre.com>
Subject: Re: [PATCH v3 4/6] usb: dwc3: Add Amlogic A1 DWC3 glue
Date: Thu, 2 Jan 2020 22:52:44 +0100	[thread overview]
Message-ID: <CAFBinCAEO=c+5oZrUmW=YhqD5tQkm0NUSbgwxHYqL2UgcK4c5Q@mail.gmail.com> (raw)
In-Reply-To: <d66abc21-1440-503b-3515-6c495bf0db80@amlogic.com>

Hello Hanjie,

On Thu, Jan 2, 2020 at 1:30 AM Hanjie Lin <hanjie.lin@amlogic.com> wrote:
[...]
> >> -               if (i == USB2_OTG_PHY) {
> >> +               if (priv->soc_id == MESON_SOC_G12A && i == USB2_OTG_PHY) {
> > on GXL we have two PHYs (0 and 1), the second one is OTG capable
> > on GXM we have three PHYs (0..2), the second one is OTG capable
> > on G12A/G12B we have two PHYs (0 and 1), the second one is OTG capable
> >
> > you already wrote that there is only one USB2 PHY on the A1 SoC
> > is really only the second PHY port ("usb2-phy1" instead of
> > "usb2-phy0") used on A1?
> > if "usb2-phy0" is correct then you don't need these checks (there are
> > more checks like this below)
>
> Actually, A1 have same phys("usb2-phy0", "usb2-phy1", "usb3-phy0") and register base with G12A.
> But A1 driver is designed to support host mode with usb2-phy1 only.
OK, thank you for clarifying this interesting decision made by the HW team

...]
> >> -       usb_role_switch_unregister(priv->role_switch);
> >> +       if (priv->soc_id == MESON_SOC_G12A)
> >> +               usb_role_switch_unregister(priv->role_switch);
> > I didn't expect this because in _probe usb_role_switch_register is still called
> > on A1 we now call usb_role_switch_register() but we never call
> > usb_role_switch_unregister()
> >
>
> Actually, usb_role_switch_register() can be called only in G12A.
>
> dwc3_meson_g12a_probe()
>          ...
>          if (priv->soc_id != MESON_SOC_G12A)
>                  goto setup_pm_runtime;
I completely missed that, thank you for clarifying it

>
> Same with second suggestion, this different SoC extra logic could avoided by add constraints
> to .yaml.
> I will do this in next version.
that would be awesome if it works out!


Martin

  reply	other threads:[~2020-01-02 21:52 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-27  6:36 [PATCH v3 0/6] arm64: meson: Add support for USB on Amlogic A1 Hanjie Lin
2019-12-27  6:36 ` [PATCH v3 1/6] dt-bindings: phy: Add Amlogic A1 USB2 PHY Bindings Hanjie Lin
2020-01-04  0:28   ` Rob Herring
2020-01-07  2:35     ` Hanjie Lin
2019-12-27  6:36 ` [PATCH v3 2/6] dt-bindings: usb: dwc3: Add the Amlogic A1 Family DWC3 Glue Bindings Hanjie Lin
2020-01-04  0:32   ` Rob Herring
2020-01-07  2:43     ` Hanjie Lin
2019-12-27  6:36 ` [PATCH v3 3/6] phy: amlogic: Add Amlogic A1 USB2 PHY Driver Hanjie Lin
2019-12-27 16:40   ` Martin Blumenstingl
2020-01-02  0:10     ` Hanjie Lin
2019-12-28  2:53   ` Chunfeng Yun
2020-01-02  0:12     ` Hanjie Lin
2019-12-27  6:36 ` [PATCH v3 4/6] usb: dwc3: Add Amlogic A1 DWC3 glue Hanjie Lin
2019-12-27 16:38   ` Martin Blumenstingl
2020-01-02  0:30     ` Hanjie Lin
2020-01-02 21:52       ` Martin Blumenstingl [this message]
2019-12-27  6:36 ` [PATCH v3 5/6] arm64: dts: meson: a1: Enable USB2 PHY Hanjie Lin
2019-12-27  6:36 ` [PATCH v3 6/6] arm64: dts: meson: a1: Enable DWC3 controller Hanjie Lin

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