From: Andy Chiu <andybnac@gmail.com>
To: Charlie Jenkins <charlie@rivosinc.com>
Cc: Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Jisheng Zhang <jszhang@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Samuel Holland <samuel.holland@sifive.com>,
Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>,
Guo Ren <guoren@kernel.org>, Evan Green <evan@rivosinc.com>,
Andy Chiu <andy.chiu@sifive.com>,
Jessica Clarke <jrtc27@jrtc27.com>,
Andrew Jones <ajones@ventanamicro.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v10 02/14] dt-bindings: cpus: add a thead vlen register length property
Date: Thu, 3 Oct 2024 00:05:37 +0800 [thread overview]
Message-ID: <CAFTtA3NwGFioVAeipkA6aCUfRY12jKFJiR7MaCpCYNjdsT7TMQ@mail.gmail.com> (raw)
In-Reply-To: <20240911-xtheadvector-v10-2-8d3930091246@rivosinc.com>
Charlie Jenkins <charlie@rivosinc.com> 於 2024年9月12日 週四 下午1:57寫道：
>
> Add a property analogous to the vlenb CSR so that software can detect
> the vector length of each CPU prior to it being brought online.
> Currently software has to assume that the vector length read from the
> boot CPU applies to all possible CPUs. On T-Head CPUs implementing
> pre-ratification vector, reading the th.vlenb CSR may produce an illegal
> instruction trap, so this property is required on such systems.
>
> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andy Chiu <andybnac@gmail.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 8edc8261241a..c0cf6cf56749 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -26,6 +26,18 @@ description: |
> allOf:
> - $ref: /schemas/cpu.yaml#
> - $ref: extensions.yaml
> + - if:
> + not:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - thead,c906
> + - thead,c910
> + - thead,c920
> + then:
> + properties:
> + thead,vlenb: false
>
> properties:
> compatible:
> @@ -95,6 +107,13 @@ properties:
> description:
> The blocksize in bytes for the Zicboz cache operations.
>
> + thead,vlenb:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + VLEN/8, the vector register length in bytes. This property is required on
> + thead systems where the vector register length is not identical on all harts, or
> + the vlenb CSR is not available.
> +
> # RISC-V has multiple properties for cache op block sizes as the sizes
> # differ between individual CBO extensions
> cache-op-block-size: false
>
> --
> 2.45.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-10-02 16:05 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-12 5:55 [PATCH v10 00/14] riscv: Add support for xtheadvector Charlie Jenkins
2024-09-12 5:55 ` [PATCH v10 01/14] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-10-02 15:07 ` Andy Chiu
2024-09-12 5:55 ` [PATCH v10 02/14] dt-bindings: cpus: add a thead vlen register length property Charlie Jenkins
2024-10-02 16:05 ` Andy Chiu [this message]
2024-09-12 5:55 ` [PATCH v10 03/14] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-11-12 2:12 ` D1 vlenb h1k0n
2024-11-12 18:03 ` Conor Dooley
2024-09-12 5:55 ` [PATCH v10 04/14] riscv: Add thead and xtheadvector as a vendor extension Charlie Jenkins
2024-09-12 5:55 ` [PATCH v10 05/14] riscv: vector: Use vlenb from DT for thead Charlie Jenkins
2024-10-02 16:34 ` Andy Chiu
2024-11-09 19:34 ` Yangyu Chen
2024-11-14 2:24 ` Charlie Jenkins
2024-09-12 5:55 ` [PATCH v10 06/14] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-10-06 16:04 ` Andy Chiu
2024-09-12 5:55 ` [PATCH v10 07/14] riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT Charlie Jenkins
2024-10-06 16:11 ` Andy Chiu
2024-09-12 5:55 ` [PATCH v10 08/14] riscv: Add xtheadvector instruction definitions Charlie Jenkins
2024-09-12 5:55 ` [PATCH v10 09/14] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-10-08 17:34 ` Andy Chiu
2024-09-12 5:55 ` [PATCH v10 10/14] riscv: hwprobe: Add thead vendor extension probing Charlie Jenkins
2024-10-02 16:59 ` Emil Renner Berthing
2024-10-29 18:00 ` Yangyu Chen
2024-09-12 5:55 ` [PATCH v10 11/14] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension Charlie Jenkins
2024-09-12 5:55 ` [PATCH v10 12/14] selftests: riscv: Fix vector tests Charlie Jenkins
2024-09-12 5:55 ` [PATCH v10 13/14] selftests: riscv: Support xtheadvector in " Charlie Jenkins
2024-09-12 5:55 ` [PATCH v10 14/14] riscv: Add ghostwrite vulnerability Charlie Jenkins
2024-09-16 17:12 ` Conor Dooley
2024-09-16 18:44 ` Charlie Jenkins
2024-09-16 18:56 ` Conor Dooley
2024-09-29 12:44 ` [PATCH v10 00/14] riscv: Add support for xtheadvector Aoba K
2024-09-30 14:53 ` Conor Dooley
2024-09-30 15:50 ` 回覆: " Aoba K
2024-09-29 16:07 ` Aoba K
2024-11-14 2:44 ` Charlie Jenkins
2025-01-21 14:19 ` nexp_0x17
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