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AJvYcCUXSqa6EmUf+KADdvGyej7t10ix14U2MLcVtpDs+UPrzXCeRpiChMPSgvunWMyR6xV/Y8jshyLuyj/RreK+@vger.kernel.org, AJvYcCUfJsTuV6ow86c/igjXVgNnxyKw3Zl+lUhUCjmR5Y1eNaZ/jKjWL2zMvYqA6gIDsma/a92kFQa4ZUP4@vger.kernel.org, AJvYcCVWkjhAaaPU7Li2WBdF7MGyNewfL5g8xckOxt9w43Pw1vVyL1nbcWobrjBPCcpweVqUM4Gz2K6mDmYV@vger.kernel.org, AJvYcCXIp8TfskynNFBr5sI0s10G3t9RcH8GN+6jenerN2g6nA+Ki25Z4DVpgBsNQd+Whu0laQb002441kxVm8gr/SAi@vger.kernel.org X-Gm-Message-State: AOJu0YxUQsdUAB/1T/XoH9utdop9uXQjeGY9P3GgVwF94/hfOHfrglJt JcwIopUgeJ9rooPffXx2KqfdydFwHdcLRMOMSh5zPQ2leMiSl+0m0rq0nL3zh85WHmIhnSsvqpX fDnYh/dBAE7C2h90tqfzRkNlES8E= X-Google-Smtp-Source: AGHT+IFUlmzbLTsFGYihjtzA3b4/xF4lQlYRCLWv50QanOiiRb9UJNd04Ll1C8wrxpzQb0JBZR9YOz+0MxaVbPy8aQQ= X-Received: by 2002:a05:690c:6d09:b0:627:778f:b0a8 with SMTP id 00721157ae682-6e2a2e37b2bmr40441297b3.42.1727885149175; Wed, 02 Oct 2024 09:05:49 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com> <20240911-xtheadvector-v10-2-8d3930091246@rivosinc.com> In-Reply-To: <20240911-xtheadvector-v10-2-8d3930091246@rivosinc.com> From: Andy Chiu Date: Thu, 3 Oct 2024 00:05:37 +0800 Message-ID: Subject: Re: [PATCH v10 02/14] dt-bindings: cpus: add a thead vlen register length property To: Charlie Jenkins Cc: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , Jessica Clarke , Andrew Jones , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Conor Dooley Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Charlie Jenkins =E6=96=BC 2024=E5=B9=B49=E6=9C=8812= =E6=97=A5 =E9=80=B1=E5=9B=9B =E4=B8=8B=E5=8D=881:57=E5=AF=AB=E9=81=93=EF=BC= =9A > > Add a property analogous to the vlenb CSR so that software can detect > the vector length of each CPU prior to it being brought online. > Currently software has to assume that the vector length read from the > boot CPU applies to all possible CPUs. On T-Head CPUs implementing > pre-ratification vector, reading the th.vlenb CSR may produce an illegal > instruction trap, so this property is required on such systems. > > Signed-off-by: Charlie Jenkins > Reviewed-by: Conor Dooley Reviewed-by: Andy Chiu > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 19 +++++++++++++++++= ++ > 1 file changed, 19 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Document= ation/devicetree/bindings/riscv/cpus.yaml > index 8edc8261241a..c0cf6cf56749 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -26,6 +26,18 @@ description: | > allOf: > - $ref: /schemas/cpu.yaml# > - $ref: extensions.yaml > + - if: > + not: > + properties: > + compatible: > + contains: > + enum: > + - thead,c906 > + - thead,c910 > + - thead,c920 > + then: > + properties: > + thead,vlenb: false > > properties: > compatible: > @@ -95,6 +107,13 @@ properties: > description: > The blocksize in bytes for the Zicboz cache operations. > > + thead,vlenb: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + VLEN/8, the vector register length in bytes. This property is requ= ired on > + thead systems where the vector register length is not identical on= all harts, or > + the vlenb CSR is not available. > + > # RISC-V has multiple properties for cache op block sizes as the sizes > # differ between individual CBO extensions > cache-op-block-size: false > > -- > 2.45.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv