From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: MIME-Version: 1.0 References: <20190129080926.36773-1-Zhiqiang.Hou@nxp.com> <20190129113910.GA7467@e107981-ln.cambridge.arm.com> In-Reply-To: <20190129113910.GA7467@e107981-ln.cambridge.arm.com> From: Subrahmanya Lingappa Date: Mon, 4 Feb 2019 19:44:25 +0530 Message-ID: Subject: Re: [PATCHv3 00/27] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Content-Type: multipart/alternative; boundary="000000000000c203850581121cd1" To: Lorenzo Pieralisi Cc: "Z.q. Hou" , "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , Leo Li , "catalin.marinas@arm.com" , "will.deacon@arm.com" , Mingkai Hu , "M.h. Lian" , Xiaowei Bao List-ID: --000000000000c203850581121cd1 Content-Type: text/plain; charset="UTF-8" Bjorn, My apologies, I was away for a while from this work. I am starting to review now. Thanks, ~subbu On Tue, Jan 29, 2019 at 5:09 PM Lorenzo Pieralisi wrote: > On Tue, Jan 29, 2019 at 08:08:28AM +0000, Z.q. Hou wrote: > > From: Hou Zhiqiang > > > > This patch set is aim to refactor the Mobiveil driver and add > > PCIe support for NXP Layerscape series SoCs integrated Mobiveil's > > PCIe Gen4 controller. > > > > Hou Zhiqiang (27): > > PCI: mobiveil: uniform the register accessors > > PCI: mobiveil: format the code without function change > > PCI: mobiveil: correct the returned error number > > PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI > > PCI: mobiveil: correct PCI base address in MEM/IO outbound windows > > PCI: mobiveil: replace the resource list iteration function > > PCI: mobiveil: use WIN_NUM_0 explicitly for CFG outbound window > > PCI: mobiveil: use the 1st inbound window for MEM inbound transactions > > PCI: mobiveil: correct inbound/outbound window setup routines > > PCI: mobiveil: fix the INTx process error > > PCI: mobiveil: only fix up the Class Code field > > PCI: mobiveil: move out the link up waiting from mobiveil_host_init > > PCI: mobiveil: move irq chained handler setup out of DT parse > > PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number > > dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to optional > > PCI: mobiveil: refactor Mobiveil PCIe Host Bridge IP driver > > PCI: mobiveil: fix the checking of valid device > > PCI: mobiveil: continue to initialize the host upon no PCIe link > > PCI: mobiveil: disabled IB and OB windows set by bootloader > > PCI: mobiveil: add Byte and Half-Word width register accessors > > PCI: mobiveil: make mobiveil_host_init can be used to re-init host > > dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller > > PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs > > PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577 > > PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451 > > arm64: dts: freescale: lx2160a: add pcie DT nodes > > arm64: defconfig: Enable CONFIG_PCI_LAYERSCAPE_GEN4 > > Subrahmanya, > > Either you review this series or I will have to drop you from > the MAINTAINERS list for this driver, I am sorry but I asked you > before to no avail. > > Thanks, > Lorenzo > > > .../bindings/pci/layerscape-pci-gen4.txt | 52 ++ > > .../devicetree/bindings/pci/mobiveil-pcie.txt | 2 + > > MAINTAINERS | 10 +- > > .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 163 ++++ > > arch/arm64/configs/defconfig | 1 + > > drivers/pci/controller/Kconfig | 11 +- > > drivers/pci/controller/Makefile | 2 +- > > drivers/pci/controller/mobiveil/Kconfig | 34 + > > drivers/pci/controller/mobiveil/Makefile | 5 + > > .../controller/mobiveil/pci-layerscape-gen4.c | 306 +++++++ > > .../controller/mobiveil/pcie-mobiveil-host.c | 640 +++++++++++++ > > .../controller/mobiveil/pcie-mobiveil-plat.c | 54 ++ > > .../pci/controller/mobiveil/pcie-mobiveil.c | 246 +++++ > > .../pci/controller/mobiveil/pcie-mobiveil.h | 229 +++++ > > drivers/pci/controller/pcie-mobiveil.c | 861 ------------------ > > 15 files changed, 1743 insertions(+), 873 deletions(-) > > create mode 100644 > Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt > > create mode 100644 drivers/pci/controller/mobiveil/Kconfig > > create mode 100644 drivers/pci/controller/mobiveil/Makefile > > create mode 100644 drivers/pci/controller/mobiveil/pci-layerscape-gen4.c > > create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil-host.c > > create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil-plat.c > > create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil.c > > create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil.h > > delete mode 100644 drivers/pci/controller/pcie-mobiveil.c > > > > -- > > 2.17.1 > > > --000000000000c203850581121cd1 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Bjorn,
My apologies, I was away for= a while from this work.
I am starting to review now.

Thanks,
~subbu

On Tue, Jan 2= 9, 2019 at 5:09 PM Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote:
On Tue, Jan 29, 2019 at 08:08:28AM +000= 0, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> This patch set is aim to refactor the Mobiveil driver and add
> PCIe support for NXP Layerscape series SoCs integrated Mobiveil's<= br> > PCIe Gen4 controller.
>
> Hou Zhiqiang (27):
>=C2=A0 =C2=A0PCI: mobiveil: uniform the register accessors
>=C2=A0 =C2=A0PCI: mobiveil: format the code without function change
>=C2=A0 =C2=A0PCI: mobiveil: correct the returned error number
>=C2=A0 =C2=A0PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI
>=C2=A0 =C2=A0PCI: mobiveil: correct PCI base address in MEM/IO outbound= windows
>=C2=A0 =C2=A0PCI: mobiveil: replace the resource list iteration functio= n
>=C2=A0 =C2=A0PCI: mobiveil: use WIN_NUM_0 explicitly for CFG outbound w= indow
>=C2=A0 =C2=A0PCI: mobiveil: use the 1st inbound window for MEM inbound = transactions
>=C2=A0 =C2=A0PCI: mobiveil: correct inbound/outbound window setup routi= nes
>=C2=A0 =C2=A0PCI: mobiveil: fix the INTx process error
>=C2=A0 =C2=A0PCI: mobiveil: only fix up the Class Code field
>=C2=A0 =C2=A0PCI: mobiveil: move out the link up waiting from mobiveil_= host_init
>=C2=A0 =C2=A0PCI: mobiveil: move irq chained handler setup out of DT pa= rse
>=C2=A0 =C2=A0PCI: mobiveil: initialize Primary/Secondary/Subordinate bu= s number
>=C2=A0 =C2=A0dt-bindings: pci: mobiveil: change gpio_slave and apb_csr = to optional
>=C2=A0 =C2=A0PCI: mobiveil: refactor Mobiveil PCIe Host Bridge IP drive= r
>=C2=A0 =C2=A0PCI: mobiveil: fix the checking of valid device
>=C2=A0 =C2=A0PCI: mobiveil: continue to initialize the host upon no PCI= e link
>=C2=A0 =C2=A0PCI: mobiveil: disabled IB and OB windows set by bootloade= r
>=C2=A0 =C2=A0PCI: mobiveil: add Byte and Half-Word width register acces= sors
>=C2=A0 =C2=A0PCI: mobiveil: make mobiveil_host_init can be used to re-i= nit host
>=C2=A0 =C2=A0dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 contro= ller
>=C2=A0 =C2=A0PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape = SoCs
>=C2=A0 =C2=A0PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577
>=C2=A0 =C2=A0PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451
>=C2=A0 =C2=A0arm64: dts: freescale: lx2160a: add pcie DT nodes
>=C2=A0 =C2=A0arm64: defconfig: Enable CONFIG_PCI_LAYERSCAPE_GEN4

Subrahmanya,

Either you review this series or I will have to drop you from
the MAINTAINERS list for this driver, I am sorry but I asked you
before to no avail.

Thanks,
Lorenzo

>=C2=A0 .../bindings/pci/layerscape-pci-gen4.txt=C2=A0 =C2=A0 =C2=A0 |= =C2=A0 52 ++
>=C2=A0 .../devicetree/bindings/pci/mobiveil-pcie.txt |=C2=A0 =C2=A02 +<= br> >=C2=A0 MAINTAINERS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 10 +-
>=C2=A0 .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 163 ++++
>=C2=A0 arch/arm64/configs/defconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A01 +
>=C2=A0 drivers/pci/controller/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 |=C2=A0 11 +-
>=C2=A0 drivers/pci/controller/Makefile=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A02 +-
>=C2=A0 drivers/pci/controller/mobiveil/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2= =A0|=C2=A0 34 +
>=C2=A0 drivers/pci/controller/mobiveil/Makefile=C2=A0 =C2=A0 =C2=A0 |= =C2=A0 =C2=A05 +
>=C2=A0 .../controller/mobiveil/pci-layerscape-gen4.c | 306 +++++++
>=C2=A0 .../controller/mobiveil/pcie-mobiveil-host.c=C2=A0 | 640 +++++++= ++++++
>=C2=A0 .../controller/mobiveil/pcie-mobiveil-plat.c=C2=A0 |=C2=A0 54 ++=
>=C2=A0 .../pci/controller/mobiveil/pcie-mobiveil.c=C2=A0 =C2=A0| 246 ++= +++
>=C2=A0 .../pci/controller/mobiveil/pcie-mobiveil.h=C2=A0 =C2=A0| 229 ++= +++
>=C2=A0 drivers/pci/controller/pcie-mobiveil.c=C2=A0 =C2=A0 =C2=A0 =C2= =A0 | 861 ------------------
>=C2=A0 15 files changed, 1743 insertions(+), 873 deletions(-)
>=C2=A0 create mode 100644 Documentation/devicetree/bindings/pci/layersc= ape-pci-gen4.txt
>=C2=A0 create mode 100644 drivers/pci/controller/mobiveil/Kconfig
>=C2=A0 create mode 100644 drivers/pci/controller/mobiveil/Makefile
>=C2=A0 create mode 100644 drivers/pci/controller/mobiveil/pci-layerscap= e-gen4.c
>=C2=A0 create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil= -host.c
>=C2=A0 create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil= -plat.c
>=C2=A0 create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil= .c
>=C2=A0 create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil= .h
>=C2=A0 delete mode 100644 drivers/pci/controller/pcie-mobiveil.c
>
> --
> 2.17.1
>
--000000000000c203850581121cd1--