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References: <20211212181906.94062-1-romain.perier@gmail.com> <20211212181906.94062-3-romain.perier@gmail.com>
In-Reply-To: <20211212181906.94062-3-romain.perier@gmail.com>
From:   Daniel Palmer <daniel@0x0f.com>
Date:   Wed, 15 Dec 2021 21:00:25 +0900
Message-ID: <CAFr9PXki8LVdjQC_4eDSuB1dmEmv2K00bWOy92cOXENEoEyeqw@mail.gmail.com>
Subject: Re: [PATCH v2 2/6] clocksource: msc313e: Add support for
 ssd20xd-based platforms
To:     Romain Perier <romain.perier@gmail.com>
Cc:     Daniel Lezcano <daniel.lezcano@linaro.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Rob Herring <robh+dt@kernel.org>,
        Russell King <linux@armlinux.org.uk>,
        DTML <devicetree@vger.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
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Hi Romain,

On Mon, 13 Dec 2021 at 03:19, Romain Perier <romain.perier@gmail.com> wrote:
>
> SSD20X family SoCs have an oscillator running at ~432Mhz for timer1 and
> timer2, while timer0 is running at 12Mhz.

I don't think this is technically true. I think the boot rom sets the
divider for timer0 so that it runs at ~12MHz.
I think the current change to only configure timer1 and timer2 is ok
but maybe the commit message should say that timer0 is configured to
be backwards compatible at boot.

Cheers,

Daniel