Re: [PATCH 3/6] clk: stm32f4: Add post divisor for I2S & SAI PLLs and Add lcd-tft clock

["Radosław Pietrzyk" <radoslaw.pietrzyk@gmail.com>]

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Wouldn't it be good to connect ltdc gate clock with lcd-tft clock to enable
the whole LCD clock chain in once ?

2016-11-07 14:05 GMT+01:00 <gabriel.fernandez@st.com>:

> From: Gabriel Fernandez <gabriel.fernandez@st.com>
>
> This patch adds post dividers of I2S & SAI PLLs.
> These dividers are managed by a dedicated register (RCC_DCKCFGR).
> The PLL should be off before a set rate.
> This patch also introduces the lcd-tft clock.
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
> ---
>  drivers/clk/clk-stm32f4.c | 27 +++++++++++++++++++++++++--
>  1 file changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
> index dda15bc..5fa5d51 100644
> --- a/drivers/clk/clk-stm32f4.c
> +++ b/drivers/clk/clk-stm32f4.c
> @@ -215,6 +215,7 @@ struct stm32f4_gate_data {
>  enum {
>         SYSTICK, FCLK, CLK_LSI, CLK_LSE, CLK_HSE_RTC, CLK_RTC,
>         PLL_VCO_I2S, PLL_VCO_SAI,
> +       CLK_LCD,
>         END_PRIMARY_CLK
>  };
>
> @@ -599,6 +600,9 @@ static struct clk_hw *clk_register_pll_div(const char
> *name,
>  static const struct clk_div_table pll_divp_table[] = {
>         { 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 },
>  };
> +static const struct clk_div_table pll_lcd_div_table[] = {
> +       { 0, 2 }, { 1, 4 }, { 2, 8 }, { 3, 16 },
> +};
>
>  /*
>   * Decode current PLL state and (statically) model the state we inherit
> from
> @@ -659,16 +663,35 @@ static struct clk_hw *stm32f4_rcc_register_pll(const
> char *pllsrc,
>                 clk_register_pll_div(data->p_name, data->vco_name, 0, reg,
>                                 16, 2, 0, pll_divp_table, pll_hw, lock);
>
> -       if (data->q_name)
> +       if (data->q_name) {
>                 clk_register_pll_div(data->q_name, data->vco_name, 0, reg,
>                                 24, 4, CLK_DIVIDER_ONE_BASED, NULL,
>                                 pll_hw, lock);
>
> -       if (data->r_name)
> +               if (data->pll_num == PLL_I2S)
> +                       clk_register_pll_div("plli2s-q-div", data->q_name,
> +                               0, base + STM32F4_RCC_DCKCFGR,
> +                               0, 5, 0, NULL, pll_hw, &stm32f4_clk_lock);
> +
> +               if (data->pll_num == PLL_SAI)
> +                       clk_register_pll_div("pllsai-q-div", data->q_name,
> +                               0, base + STM32F4_RCC_DCKCFGR,
> +                               8, 5, 0, NULL, pll_hw, &stm32f4_clk_lock);
> +       }
> +
> +       if (data->r_name) {
>                 clk_register_pll_div(data->r_name, data->vco_name, 0, reg,
>                                 28, 3, CLK_DIVIDER_ONE_BASED, NULL,
> pll_hw,
>                                 lock);
>
> +               if (data->pll_num == PLL_SAI)
> +                       clks[CLK_LCD] = clk_register_pll_div("lcd-tft",
> +                                       data->r_name, CLK_SET_RATE_PARENT,
> +                                       base + STM32F4_RCC_DCKCFGR, 16, 2,
> 0,
> +                                       pll_lcd_div_table, pll_hw,
> +                                       &stm32f4_clk_lock);
> +       }
> +
>         return pll_hw;
>  }
>
> --
> 1.9.1
>
>
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