From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: MIME-Version: 1.0 In-Reply-To: <1478523943-23142-4-git-send-email-gabriel.fernandez@st.com> References: <1478523943-23142-1-git-send-email-gabriel.fernandez@st.com> <1478523943-23142-4-git-send-email-gabriel.fernandez@st.com> From: =?UTF-8?Q?Rados=C5=82aw_Pietrzyk?= Date: Mon, 7 Nov 2016 14:48:15 +0100 Message-ID: Subject: Re: [PATCH 3/6] clk: stm32f4: Add post divisor for I2S & SAI PLLs and Add lcd-tft clock Content-Type: multipart/alternative; boundary=94eb2c0d90589be52f0540b64687 To: Gabriel FERNANDEZ Cc: Rob Herring , Mark Rutland , Russell King , Maxime Coquelin , Alexandre Torgue , Michael Turquette , Stephen Boyd , Nicolas Pitre , Arnd Bergmann , Daniel Thompson , Andrea Merello , devicetree@vger.kernel.org, amelie.delaunay@st.com, kernel@stlinux.com, olivier.bideau@st.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, ludovic.barre@st.com, linux-arm-kernel@lists.infradead.org List-ID: --94eb2c0d90589be52f0540b64687 Content-Type: text/plain; charset=UTF-8 Wouldn't it be good to connect ltdc gate clock with lcd-tft clock to enable the whole LCD clock chain in once ? 2016-11-07 14:05 GMT+01:00 : > From: Gabriel Fernandez > > This patch adds post dividers of I2S & SAI PLLs. > These dividers are managed by a dedicated register (RCC_DCKCFGR). > The PLL should be off before a set rate. > This patch also introduces the lcd-tft clock. > > Signed-off-by: Gabriel Fernandez > --- > drivers/clk/clk-stm32f4.c | 27 +++++++++++++++++++++++++-- > 1 file changed, 25 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c > index dda15bc..5fa5d51 100644 > --- a/drivers/clk/clk-stm32f4.c > +++ b/drivers/clk/clk-stm32f4.c > @@ -215,6 +215,7 @@ struct stm32f4_gate_data { > enum { > SYSTICK, FCLK, CLK_LSI, CLK_LSE, CLK_HSE_RTC, CLK_RTC, > PLL_VCO_I2S, PLL_VCO_SAI, > + CLK_LCD, > END_PRIMARY_CLK > }; > > @@ -599,6 +600,9 @@ static struct clk_hw *clk_register_pll_div(const char > *name, > static const struct clk_div_table pll_divp_table[] = { > { 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 }, > }; > +static const struct clk_div_table pll_lcd_div_table[] = { > + { 0, 2 }, { 1, 4 }, { 2, 8 }, { 3, 16 }, > +}; > > /* > * Decode current PLL state and (statically) model the state we inherit > from > @@ -659,16 +663,35 @@ static struct clk_hw *stm32f4_rcc_register_pll(const > char *pllsrc, > clk_register_pll_div(data->p_name, data->vco_name, 0, reg, > 16, 2, 0, pll_divp_table, pll_hw, lock); > > - if (data->q_name) > + if (data->q_name) { > clk_register_pll_div(data->q_name, data->vco_name, 0, reg, > 24, 4, CLK_DIVIDER_ONE_BASED, NULL, > pll_hw, lock); > > - if (data->r_name) > + if (data->pll_num == PLL_I2S) > + clk_register_pll_div("plli2s-q-div", data->q_name, > + 0, base + STM32F4_RCC_DCKCFGR, > + 0, 5, 0, NULL, pll_hw, &stm32f4_clk_lock); > + > + if (data->pll_num == PLL_SAI) > + clk_register_pll_div("pllsai-q-div", data->q_name, > + 0, base + STM32F4_RCC_DCKCFGR, > + 8, 5, 0, NULL, pll_hw, &stm32f4_clk_lock); > + } > + > + if (data->r_name) { > clk_register_pll_div(data->r_name, data->vco_name, 0, reg, > 28, 3, CLK_DIVIDER_ONE_BASED, NULL, > pll_hw, > lock); > > + if (data->pll_num == PLL_SAI) > + clks[CLK_LCD] = clk_register_pll_div("lcd-tft", > + data->r_name, CLK_SET_RATE_PARENT, > + base + STM32F4_RCC_DCKCFGR, 16, 2, > 0, > + pll_lcd_div_table, pll_hw, > + &stm32f4_clk_lock); > + } > + > return pll_hw; > } > > -- > 1.9.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > --94eb2c0d90589be52f0540b64687 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
Wouldn't it be good to connect ltdc gate clock with lc= d-tft clock to enable the whole LCD clock chain in once ?=C2=A0

2016-11-07 14:05 GMT+01= :00 <gabriel.fernandez@st.com>:
From: Gabriel Fernandez <gabriel.fernandez@st.com>

This patch adds post dividers of I2S & SAI PLLs.
These dividers are managed by a dedicated register (RCC_DCKCFGR).
The PLL should be off before a set rate.
This patch also introduces the lcd-tft clock.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
=C2=A0drivers/clk/clk-stm32f4.c | 27 +++++++++++++++++++++++++--
=C2=A01 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index dda15bc..5fa5d51 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -215,6 +215,7 @@ struct stm32f4_gate_data {
=C2=A0enum {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 SYSTICK, FCLK, CLK_LSI, CLK_LSE, CLK_HSE_RTC, C= LK_RTC,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 PLL_VCO_I2S, PLL_VCO_SAI,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0CLK_LCD,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 END_PRIMARY_CLK
=C2=A0};

@@ -599,6 +600,9 @@ static struct clk_hw *clk_register_pll_div(const char *= name,
=C2=A0static const struct clk_div_table pll_divp_table[] =3D {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 { 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 },
=C2=A0};
+static const struct clk_div_table pll_lcd_div_table[] =3D {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0{ 0, 2 }, { 1, 4 }, { 2, 8 }, { 3, 16 },
+};

=C2=A0/*
=C2=A0 * Decode current PLL state and (statically) model the state we inher= it from
@@ -659,16 +663,35 @@ static struct clk_hw *stm32f4_rcc_register_pll(c= onst char *pllsrc,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 clk_register_pll_di= v(data->p_name, data->vco_name, 0, reg,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 16, 2, 0, pll_divp_table, pll_hw, lo= ck);

-=C2=A0 =C2=A0 =C2=A0 =C2=A0if (data->q_name)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (data->q_name) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 clk_register_pll_di= v(data->q_name, data->vco_name, 0, reg,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 24, 4, CLK_DIVIDER_ONE_BASED, NULL,<= br> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 pll_hw, lock);

-=C2=A0 =C2=A0 =C2=A0 =C2=A0if (data->r_name)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (data->pll_nu= m =3D=3D PLL_I2S)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0clk_register_pll_div("plli2s-q-div", data->q_na= me,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00, base + STM32F4_RCC_DCKCFGR,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00, 5, 0, NULL, pll_hw, &stm32f4_c= lk_lock);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (data->pll_nu= m =3D=3D PLL_SAI)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0clk_register_pll_div("pllsai-q-div", data->q_na= me,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00, base + STM32F4_RCC_DCKCFGR,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A08, 5, 0, NULL, pll_hw, &stm32f4_c= lk_lock);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (data->r_name) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 clk_register_pll_di= v(data->r_name, data->vco_name, 0, reg,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 28, 3, CLK_DIVIDER_ONE_BASED, NULL,= =C2=A0 pll_hw,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 lock);

+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (data->pll_nu= m =3D=3D PLL_SAI)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0clks[CLK_LCD] =3D clk_register_pll_div("lcd-tft",<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0data->= r_name, CLK_SET_RATE_PARENT,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0base + ST= M32F4_RCC_DCKCFGR, 16, 2, 0,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pll_lcd_d= iv_table, pll_hw,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&stm3= 2f4_clk_lock);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+
=C2=A0 =C2=A0 =C2=A0 =C2=A0 return pll_hw;
=C2=A0}

--
1.9.1


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