[PATCH v3 0/2] ARM: at91: remove phy fixup for sama5d3xek boards

[PATCH v3 0/2] ARM: at91: remove phy fixup for sama5d3xek boards

[Boris BREZILLON]

Hello,

This patch removes a board specific hook for sama5d3xek boards from the
sama5d3 generic DT board file.

This hook (which register a phy fixup configuring board specific delays
in the ksz9021 ethernet phy) is now replaced by the appropriate DT
properties definitions in the sama5d3xcm.dtsi file.

Best Regards,

Boris

Changes since v2:
 - define 2 phy nodes to handle Ronetix and Embest HW designs

Changes since v1:
 - fix txc-skew-ps and rxc-skew-ps delays
 - remove phy address info to handle Ronetix and Embest HW designs

Boris BREZILLON (2):
  ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek
    boards
  ARM: at91: remove phy fixup for sama5d3xek boards

 arch/arm/boot/dts/sama5d3xcm.dtsi   | 30 ++++++++++++++++++++++++++++++
 arch/arm/mach-at91/board-dt-sama5.c | 22 ----------------------
 2 files changed, 30 insertions(+), 22 deletions(-)

-- 
1.8.3.2

[PATCH v3 1/2] ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards

[Boris BREZILLON]

Add ethernet-phy nodes and specify phy interrupt (connected to pin PB25)
and board specific timing configs.

Atmel has two different HW designs for its CPU modules: the first one
(produced by Embest) is connecting PHYAD[0-2] pins to pull up resistors
and the other one (produced by Ronetix) is connecting PHYAD0 to a pull up
resistor and PHYAD[1-2] to pull down resistors.
As a result, Ronetix design will have its PHY available at address 0x1 and
Embest design at 0x7.
By defining both phys we're letting the phy core detect the one actually
available on the MDIO bus.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
---

Florian, I dropped your Reviewed-by tag because this patch has slightly
changed.


 arch/arm/boot/dts/sama5d3xcm.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index b0b1331..755369e 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -34,6 +34,36 @@
 
 			macb0: ethernet@f0028000 {
 				phy-mode = "rgmii";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ethernet-phy@1 {
+					reg = <0x1>;
+					interrupt-parent = <&pioB>;
+					interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+					txen-skew-ps = <800>;
+					txc-skew-ps = <3000>;
+					rxdv-skew-ps = <400>;
+					rxc-skew-ps = <3000>;
+					rxd0-skew-ps = <400>;
+					rxd1-skew-ps = <400>;
+					rxd2-skew-ps = <400>;
+					rxd3-skew-ps = <400>;
+				};
+
+				ethernet-phy@7 {
+					reg = <0x7>;
+					interrupt-parent = <&pioB>;
+					interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+					txen-skew-ps = <800>;
+					txc-skew-ps = <3000>;
+					rxdv-skew-ps = <400>;
+					rxc-skew-ps = <3000>;
+					rxd0-skew-ps = <400>;
+					rxd1-skew-ps = <400>;
+					rxd2-skew-ps = <400>;
+					rxd3-skew-ps = <400>;
+				};
 			};
 
 			pmc: pmc@fffffc00 {
-- 
1.8.3.2

Re: [PATCH v3 1/2] ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards

[Bo Shen]

Hi Boris,

On 07/11/2014 03:59 AM, Boris BREZILLON wrote:
> Add ethernet-phy nodes and specify phy interrupt (connected to pin PB25)
> and board specific timing configs.
>
> Atmel has two different HW designs for its CPU modules: the first one
> (produced by Embest) is connecting PHYAD[0-2] pins to pull up resistors
> and the other one (produced by Ronetix) is connecting PHYAD0 to a pull up
> resistor and PHYAD[1-2] to pull down resistors.
> As a result, Ronetix design will have its PHY available at address 0x1 and
> Embest design at 0x7.
> By defining both phys we're letting the phy core detect the one actually
> available on the MDIO bus.
>
> Signed-off-by: Boris BREZILLON <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>

For this patch series, test OK on both Embest (sama5d34ek) and Ronetix 
(sama5d33ek).

Tested-by: Bo Shen <voice.shen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>

> ---
>
> Florian, I dropped your Reviewed-by tag because this patch has slightly
> changed.
>
>
>   arch/arm/boot/dts/sama5d3xcm.dtsi | 30 ++++++++++++++++++++++++++++++
>   1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
> index b0b1331..755369e 100644
> --- a/arch/arm/boot/dts/sama5d3xcm.dtsi
> +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
> @@ -34,6 +34,36 @@
>
>   			macb0: ethernet@f0028000 {
>   				phy-mode = "rgmii";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				ethernet-phy@1 {
> +					reg = <0x1>;
> +					interrupt-parent = <&pioB>;
> +					interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
> +					txen-skew-ps = <800>;
> +					txc-skew-ps = <3000>;
> +					rxdv-skew-ps = <400>;
> +					rxc-skew-ps = <3000>;
> +					rxd0-skew-ps = <400>;
> +					rxd1-skew-ps = <400>;
> +					rxd2-skew-ps = <400>;
> +					rxd3-skew-ps = <400>;
> +				};
> +
> +				ethernet-phy@7 {
> +					reg = <0x7>;
> +					interrupt-parent = <&pioB>;
> +					interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
> +					txen-skew-ps = <800>;
> +					txc-skew-ps = <3000>;
> +					rxdv-skew-ps = <400>;
> +					rxc-skew-ps = <3000>;
> +					rxd0-skew-ps = <400>;
> +					rxd1-skew-ps = <400>;
> +					rxd2-skew-ps = <400>;
> +					rxd3-skew-ps = <400>;
> +				};
>   			};
>
>   			pmc: pmc@fffffc00 {
>

Best Regards,
Bo Shen

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Re: [PATCH v3 1/2] ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards

[Nicolas Ferre]

On 10/07/2014 21:59, Boris BREZILLON :
> Add ethernet-phy nodes and specify phy interrupt (connected to pin PB25)
> and board specific timing configs.
> 
> Atmel has two different HW designs for its CPU modules: the first one
> (produced by Embest) is connecting PHYAD[0-2] pins to pull up resistors
> and the other one (produced by Ronetix) is connecting PHYAD0 to a pull up
> resistor and PHYAD[1-2] to pull down resistors.
> As a result, Ronetix design will have its PHY available at address 0x1 and
> Embest design at 0x7.
> By defining both phys we're letting the phy core detect the one actually
> available on the MDIO bus.
> 
> Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
> ---
> 
> Florian, I dropped your Reviewed-by tag because this patch has slightly
> changed.

Hi Florian,

I would like to have your Ack on this one as we discussed this solution
with you.

Thanks, bye,


>  arch/arm/boot/dts/sama5d3xcm.dtsi | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
> index b0b1331..755369e 100644
> --- a/arch/arm/boot/dts/sama5d3xcm.dtsi
> +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
> @@ -34,6 +34,36 @@
>  
>  			macb0: ethernet@f0028000 {
>  				phy-mode = "rgmii";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				ethernet-phy@1 {
> +					reg = <0x1>;
> +					interrupt-parent = <&pioB>;
> +					interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
> +					txen-skew-ps = <800>;
> +					txc-skew-ps = <3000>;
> +					rxdv-skew-ps = <400>;
> +					rxc-skew-ps = <3000>;
> +					rxd0-skew-ps = <400>;
> +					rxd1-skew-ps = <400>;
> +					rxd2-skew-ps = <400>;
> +					rxd3-skew-ps = <400>;
> +				};
> +
> +				ethernet-phy@7 {
> +					reg = <0x7>;
> +					interrupt-parent = <&pioB>;
> +					interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
> +					txen-skew-ps = <800>;
> +					txc-skew-ps = <3000>;
> +					rxdv-skew-ps = <400>;
> +					rxc-skew-ps = <3000>;
> +					rxd0-skew-ps = <400>;
> +					rxd1-skew-ps = <400>;
> +					rxd2-skew-ps = <400>;
> +					rxd3-skew-ps = <400>;
> +				};
>  			};
>  
>  			pmc: pmc@fffffc00 {
> 


-- 
Nicolas Ferre

Re: [PATCH v3 1/2] ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards

[Florian Fainelli]

[-- Attachment #1: Type: text/plain, Size: 3389 bytes --]

On Jul 18, 2014 7:21 AM, "Nicolas Ferre" <nicolas.ferre@atmel.com> wrote:
>
> On 10/07/2014 21:59, Boris BREZILLON :
> > Add ethernet-phy nodes and specify phy interrupt (connected to pin PB25)
> > and board specific timing configs.
> >
> > Atmel has two different HW designs for its CPU modules: the first one
> > (produced by Embest) is connecting PHYAD[0-2] pins to pull up resistors
> > and the other one (produced by Ronetix) is connecting PHYAD0 to a pull
up
> > resistor and PHYAD[1-2] to pull down resistors.
> > As a result, Ronetix design will have its PHY available at address 0x1
and
> > Embest design at 0x7.
> > By defining both phys we're letting the phy core detect the one actually
> > available on the MDIO bus.
> >
> > Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
> > ---
> >
> > Florian, I dropped your Reviewed-by tag because this patch has slightly
> > changed.
>
> Hi Florian,
>
> I would like to have your Ack on this one as we discussed this solution
> with you.

Acked-by: Florian Fainelli <f.fainelli@gmail.com>

>
> Thanks, bye,
>
>
> >  arch/arm/boot/dts/sama5d3xcm.dtsi | 30 ++++++++++++++++++++++++++++++
> >  1 file changed, 30 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi
b/arch/arm/boot/dts/sama5d3xcm.dtsi
> > index b0b1331..755369e 100644
> > --- a/arch/arm/boot/dts/sama5d3xcm.dtsi
> > +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
> > @@ -34,6 +34,36 @@
> >
> >                       macb0: ethernet@f0028000 {
> >                               phy-mode = "rgmii";
> > +                             #address-cells = <1>;
> > +                             #size-cells = <0>;
> > +
> > +                             ethernet-phy@1 {
> > +                                     reg = <0x1>;
> > +                                     interrupt-parent = <&pioB>;
> > +                                     interrupts = <25
IRQ_TYPE_EDGE_FALLING>;
> > +                                     txen-skew-ps = <800>;
> > +                                     txc-skew-ps = <3000>;
> > +                                     rxdv-skew-ps = <400>;
> > +                                     rxc-skew-ps = <3000>;
> > +                                     rxd0-skew-ps = <400>;
> > +                                     rxd1-skew-ps = <400>;
> > +                                     rxd2-skew-ps = <400>;
> > +                                     rxd3-skew-ps = <400>;
> > +                             };
> > +
> > +                             ethernet-phy@7 {
> > +                                     reg = <0x7>;
> > +                                     interrupt-parent = <&pioB>;
> > +                                     interrupts = <25
IRQ_TYPE_EDGE_FALLING>;
> > +                                     txen-skew-ps = <800>;
> > +                                     txc-skew-ps = <3000>;
> > +                                     rxdv-skew-ps = <400>;
> > +                                     rxc-skew-ps = <3000>;
> > +                                     rxd0-skew-ps = <400>;
> > +                                     rxd1-skew-ps = <400>;
> > +                                     rxd2-skew-ps = <400>;
> > +                                     rxd3-skew-ps = <400>;
> > +                             };
> >                       };
> >
> >                       pmc: pmc@fffffc00 {
> >
>
>
> --
> Nicolas Ferre

[-- Attachment #2: Type: text/html, Size: 5111 bytes --]

Re: [PATCH v3 1/2] ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards

[Florian Fainelli]

2014-07-18 7:21 GMT-07:00 Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>:
> On 10/07/2014 21:59, Boris BREZILLON :
>> Add ethernet-phy nodes and specify phy interrupt (connected to pin PB25)
>> and board specific timing configs.
>>
>> Atmel has two different HW designs for its CPU modules: the first one
>> (produced by Embest) is connecting PHYAD[0-2] pins to pull up resistors
>> and the other one (produced by Ronetix) is connecting PHYAD0 to a pull up
>> resistor and PHYAD[1-2] to pull down resistors.
>> As a result, Ronetix design will have its PHY available at address 0x1 and
>> Embest design at 0x7.
>> By defining both phys we're letting the phy core detect the one actually
>> available on the MDIO bus.
>>
>> Signed-off-by: Boris BREZILLON <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>> ---
>>
>> Florian, I dropped your Reviewed-by tag because this patch has slightly
>> changed.
>
> Hi Florian,
>
> I would like to have your Ack on this one as we discussed this solution
> with you.

Acked-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

>
> Thanks, bye,
>
>
>>  arch/arm/boot/dts/sama5d3xcm.dtsi | 30 ++++++++++++++++++++++++++++++
>>  1 file changed, 30 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
>> index b0b1331..755369e 100644
>> --- a/arch/arm/boot/dts/sama5d3xcm.dtsi
>> +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
>> @@ -34,6 +34,36 @@
>>
>>                       macb0: ethernet@f0028000 {
>>                               phy-mode = "rgmii";
>> +                             #address-cells = <1>;
>> +                             #size-cells = <0>;
>> +
>> +                             ethernet-phy@1 {
>> +                                     reg = <0x1>;
>> +                                     interrupt-parent = <&pioB>;
>> +                                     interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
>> +                                     txen-skew-ps = <800>;
>> +                                     txc-skew-ps = <3000>;
>> +                                     rxdv-skew-ps = <400>;
>> +                                     rxc-skew-ps = <3000>;
>> +                                     rxd0-skew-ps = <400>;
>> +                                     rxd1-skew-ps = <400>;
>> +                                     rxd2-skew-ps = <400>;
>> +                                     rxd3-skew-ps = <400>;
>> +                             };
>> +
>> +                             ethernet-phy@7 {
>> +                                     reg = <0x7>;
>> +                                     interrupt-parent = <&pioB>;
>> +                                     interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
>> +                                     txen-skew-ps = <800>;
>> +                                     txc-skew-ps = <3000>;
>> +                                     rxdv-skew-ps = <400>;
>> +                                     rxc-skew-ps = <3000>;
>> +                                     rxd0-skew-ps = <400>;
>> +                                     rxd1-skew-ps = <400>;
>> +                                     rxd2-skew-ps = <400>;
>> +                                     rxd3-skew-ps = <400>;
>> +                             };
>>                       };
>>
>>                       pmc: pmc@fffffc00 {
>>
>
>
> --
> Nicolas Ferre



-- 
Florian
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[PATCH v3 2/2] ARM: at91: remove phy fixup for sama5d3xek boards

[Boris BREZILLON]

These board specific delays are now configured through micrel's specific
DT bindings (see Documentation/devicetree/bindings/net/micrel-ksz9021.txt).

Remove this phy fixup registration from sama5 DT machine file to keep it
as generic as possible.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
---
 arch/arm/mach-at91/board-dt-sama5.c | 22 ----------------------
 1 file changed, 22 deletions(-)

diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 075ec05..70b2504 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -46,30 +46,8 @@ static void __init at91_dt_init_irq(void)
 	of_irq_init(irq_of_match);
 }
 
-static int ksz9021rn_phy_fixup(struct phy_device *phy)
-{
-	int value;
-
-	/* Set delay values */
-	value = MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW | 0x8000;
-	phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value);
-	value = 0xF2F4;
-	phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value);
-	value = MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW | 0x8000;
-	phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value);
-	value = 0x2222;
-	phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value);
-
-	return 0;
-}
-
 static void __init sama5_dt_device_init(void)
 {
-	if (of_machine_is_compatible("atmel,sama5d3xcm") &&
-	    IS_ENABLED(CONFIG_PHYLIB))
-		phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
-			ksz9021rn_phy_fixup);
-
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-- 
1.8.3.2

Re: [PATCH v3 0/2] ARM: at91: remove phy fixup for sama5d3xek boards

[Nicolas Ferre]

On 10/07/2014 21:59, Boris BREZILLON :
> Hello,
> 
> This patch removes a board specific hook for sama5d3xek boards from the
> sama5d3 generic DT board file.
> 
> This hook (which register a phy fixup configuring board specific delays
> in the ksz9021 ethernet phy) is now replaced by the appropriate DT
> properties definitions in the sama5d3xcm.dtsi file.
> 
> Best Regards,

On the whole series:


Acked-by: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>


> Changes since v2:
>  - define 2 phy nodes to handle Ronetix and Embest HW designs
> 
> Changes since v1:
>  - fix txc-skew-ps and rxc-skew-ps delays
>  - remove phy address info to handle Ronetix and Embest HW designs
> 
> Boris BREZILLON (2):
>   ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek
>     boards
>   ARM: at91: remove phy fixup for sama5d3xek boards
> 
>  arch/arm/boot/dts/sama5d3xcm.dtsi   | 30 ++++++++++++++++++++++++++++++
>  arch/arm/mach-at91/board-dt-sama5.c | 22 ----------------------
>  2 files changed, 30 insertions(+), 22 deletions(-)
> 


-- 
Nicolas Ferre
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