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Thu, 04 Sep 2025 21:11:59 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250829091913.131528-1-laura.nao@collabora.com> <20250829091913.131528-6-laura.nao@collabora.com> In-Reply-To: <20250829091913.131528-6-laura.nao@collabora.com> From: Chen-Yu Tsai Date: Fri, 5 Sep 2025 12:11:48 +0800 X-Gm-Features: Ac12FXxJqW2o_w5uvmk3WVayIoiyKNEplrPyOCeaEvIjyu6tO3A5A0cEjAtjJqA Message-ID: Subject: Re: [PATCH v5 05/27] clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC To: Laura Nao Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, richardcochran@gmail.com, guangjie.song@mediatek.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, kernel@collabora.com, =?UTF-8?B?TsOtY29sYXMgRiAuIFIgLiBBIC4gUHJhZG8=?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Aug 29, 2025 at 5:21=E2=80=AFPM Laura Nao = wrote: > > MT8196 use a HW voter for mux gate enable/disable control, along with a > FENC status bit to check the status. Voting is performed using > set/clr/upd registers, with a status bit used to verify the vote state. > Add new set of mux gate clock operations with support for voting via > set/clr/upd regs and FENC status logic. > > Reviewed-by: N=C3=ADcolas F. R. A. Prado > Reviewed-by: AngeloGioacchino Del Regno > Signed-off-by: Laura Nao > --- > drivers/clk/mediatek/clk-mtk.h | 2 + > drivers/clk/mediatek/clk-mux.c | 73 +++++++++++++++++++++++++++++++++- > drivers/clk/mediatek/clk-mux.h | 42 +++++++++++++++++++ > 3 files changed, 116 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mt= k.h > index 11962fac43ea..c381d6a6d908 100644 > --- a/drivers/clk/mediatek/clk-mtk.h > +++ b/drivers/clk/mediatek/clk-mtk.h > @@ -20,6 +20,8 @@ > > #define MHZ (1000 * 1000) > > +#define MTK_WAIT_HWV_DONE_US 30 > + > struct platform_device; > > /* > diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mu= x.c > index 3931d157b262..2c2679e158e7 100644 > --- a/drivers/clk/mediatek/clk-mux.c > +++ b/drivers/clk/mediatek/clk-mux.c > @@ -8,6 +8,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -15,6 +16,7 @@ > #include > #include > > +#include "clk-mtk.h" > #include "clk-mux.h" > > #define MTK_WAIT_FENC_DONE_US 30 > @@ -22,6 +24,7 @@ > struct mtk_clk_mux { > struct clk_hw hw; > struct regmap *regmap; > + struct regmap *regmap_hwv; > const struct mtk_mux *data; > spinlock_t *lock; > bool reparent; > @@ -119,6 +122,41 @@ static int mtk_clk_mux_is_enabled(struct clk_hw *hw) > return (val & BIT(mux->data->gate_shift)) =3D=3D 0; > } > > +static int mtk_clk_mux_hwv_fenc_enable(struct clk_hw *hw) > +{ > + struct mtk_clk_mux *mux =3D to_mtk_clk_mux(hw); > + u32 val; > + int ret; > + > + regmap_write(mux->regmap_hwv, mux->data->hwv_set_ofs, > + BIT(mux->data->gate_shift)); > + > + ret =3D regmap_read_poll_timeout_atomic(mux->regmap_hwv, mux->dat= a->hwv_sta_ofs, > + val, val & BIT(mux->data->g= ate_shift), 0, > + MTK_WAIT_HWV_DONE_US); > + if (ret) > + return ret; > + > + ret =3D regmap_read_poll_timeout_atomic(mux->regmap, mux->data->f= enc_sta_mon_ofs, > + val, val & BIT(mux->data->f= enc_shift), 1, > + MTK_WAIT_FENC_DONE_US); > + > + return ret; > +} > + > +static void mtk_clk_mux_hwv_disable(struct clk_hw *hw) > +{ > + struct mtk_clk_mux *mux =3D to_mtk_clk_mux(hw); > + u32 val; > + > + regmap_write(mux->regmap_hwv, mux->data->hwv_clr_ofs, > + BIT(mux->data->gate_shift)); > + > + regmap_read_poll_timeout_atomic(mux->regmap_hwv, mux->data->hwv_s= ta_ofs, > + val, (val & BIT(mux->data->gate_s= hift)), > + 0, MTK_WAIT_HWV_DONE_US); > +} > + > static u8 mtk_clk_mux_get_parent(struct clk_hw *hw) > { > struct mtk_clk_mux *mux =3D to_mtk_clk_mux(hw); > @@ -190,6 +228,14 @@ static int mtk_clk_mux_determine_rate(struct clk_hw = *hw, > return clk_mux_determine_rate_flags(hw, req, mux->data->flags); > } > > +static bool mtk_clk_mux_uses_hwv(const struct clk_ops *ops) > +{ > + if (ops =3D=3D &mtk_mux_gate_hwv_fenc_clr_set_upd_ops) > + return true; > + > + return false; > +} > + > const struct clk_ops mtk_mux_clr_set_upd_ops =3D { > .get_parent =3D mtk_clk_mux_get_parent, > .set_parent =3D mtk_clk_mux_set_parent_setclr_lock, > @@ -217,9 +263,20 @@ const struct clk_ops mtk_mux_gate_fenc_clr_set_upd_o= ps =3D { > }; > EXPORT_SYMBOL_GPL(mtk_mux_gate_fenc_clr_set_upd_ops); > > +const struct clk_ops mtk_mux_gate_hwv_fenc_clr_set_upd_ops =3D { > + .enable =3D mtk_clk_mux_hwv_fenc_enable, > + .disable =3D mtk_clk_mux_hwv_disable, > + .is_enabled =3D mtk_clk_mux_fenc_is_enabled, > + .get_parent =3D mtk_clk_mux_get_parent, > + .set_parent =3D mtk_clk_mux_set_parent_setclr_lock, > + .determine_rate =3D mtk_clk_mux_determine_rate, > +}; > +EXPORT_SYMBOL_GPL(mtk_mux_gate_hwv_fenc_clr_set_upd_ops); > + > static struct clk_hw *mtk_clk_register_mux(struct device *dev, > const struct mtk_mux *mux, > struct regmap *regmap, > + struct regmap *regmap_hwv, > spinlock_t *lock) > { > struct mtk_clk_mux *clk_mux; > @@ -235,8 +292,14 @@ static struct clk_hw *mtk_clk_register_mux(struct de= vice *dev, > init.parent_names =3D mux->parent_names; > init.num_parents =3D mux->num_parents; > init.ops =3D mux->ops; > + if (mtk_clk_mux_uses_hwv(init.ops) && !regmap_hwv) { > + return dev_err_ptr_probe( > + dev, -ENXIO, > + "regmap not found for hardware voter clocks\n"); > + } Nit: The braces aren't really needed. But no need to respin just for this. Reviewed-by: Chen-Yu Tsai