[PATCH v3 0/5] IIO-based thermal sensor driver for Allwinner H3 SoC

[PATCH v3 0/5] IIO-based thermal sensor driver for Allwinner H3 SoC

[Icenowy Zheng]

Allwiner H3 SoC has a thermal sensor, which is a large refactored version of
the old Allwinner "GPADC" (although it have already only thermal part left
in A33).

This patch tried to add support for the sensor in H3 based on the A33 thermal
sensor driver by Quentin Schulz, which is already merged.

Icenowy Zheng (5):
  dt-bindings: update the Allwinner GPADC device tree binding for H3
  iio: adc: sun4i-gpadc-iio: rename A23/A33-specified registers to
    contain A23
  iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor
  ARM: sun8i: h3: add support for the thermal sensor in H3
  ARM: sun8i: h3: add partial CPU thermal zone

 .../devicetree/bindings/mfd/sun4i-gpadc.txt        |  25 ++-
 arch/arm/boot/dts/sun8i-h3.dtsi                    |  26 +++
 drivers/iio/adc/sun4i-gpadc-iio.c                  | 228 +++++++++++++++++----
 include/linux/mfd/sun4i-gpadc.h                    |  33 ++-
 4 files changed, 267 insertions(+), 45 deletions(-)

-- 
2.13.0

[PATCH v3 2/5] iio: adc: sun4i-gpadc-iio: rename A23/A33-specified registers to contain A23

[Icenowy Zheng]

As the H3 SoC, which is also in sun8i line, has totally different
register map for the thermal sensor (a cut down version of GPADC), we
should rename A23/A33-specified registers to contain A23, in order to
prevent obfuscation with H3 registers. Currently these registers are
only prefixed "SUN8I", not "SUN8I_A23".

Add "_A23" after "SUN8I" on the register names.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 drivers/iio/adc/sun4i-gpadc-iio.c | 2 +-
 include/linux/mfd/sun4i-gpadc.h   | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c
index 81d4c39e414a..41769bc6a429 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -88,7 +88,7 @@ static const struct gpadc_data sun6i_gpadc_data = {
 static const struct gpadc_data sun8i_a33_gpadc_data = {
 	.temp_offset = -1662,
 	.temp_scale = 162,
-	.tp_mode_en = SUN8I_GPADC_CTRL1_CHOP_TEMP_EN,
+	.tp_mode_en = SUN8I_A23_GPADC_CTRL1_CHOP_TEMP_EN,
 };
 
 struct sun4i_gpadc_iio {
diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h
index 139872c2e0fe..d31d962bb7d8 100644
--- a/include/linux/mfd/sun4i-gpadc.h
+++ b/include/linux/mfd/sun4i-gpadc.h
@@ -38,9 +38,9 @@
 #define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x)		(GENMASK(3, 0) & BIT(x))
 #define SUN6I_GPADC_CTRL1_ADC_CHAN_MASK			GENMASK(3, 0)
 
-/* TP_CTRL1 bits for sun8i SoCs */
-#define SUN8I_GPADC_CTRL1_CHOP_TEMP_EN			BIT(8)
-#define SUN8I_GPADC_CTRL1_GPADC_CALI_EN			BIT(7)
+/* TP_CTRL1 bits for sun8i A23/A33 SoCs */
+#define SUN8I_A23_GPADC_CTRL1_CHOP_TEMP_EN		BIT(8)
+#define SUN8I_A23_GPADC_CTRL1_GPADC_CALI_EN		BIT(7)
 
 #define SUN4I_GPADC_CTRL2				0x08
 
-- 
2.13.0

Re: [linux-sunxi] [PATCH v3 2/5] iio: adc: sun4i-gpadc-iio: rename A23/A33-specified registers to contain A23

[Chen-Yu Tsai]

On Sun, Jul 23, 2017 at 10:13 PM, Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org> wrote:
> As the H3 SoC, which is also in sun8i line, has totally different
> register map for the thermal sensor (a cut down version of GPADC), we
> should rename A23/A33-specified registers to contain A23, in order to
> prevent obfuscation with H3 registers. Currently these registers are
> only prefixed "SUN8I", not "SUN8I_A23".
>
> Add "_A23" after "SUN8I" on the register names.

Nit: the compatible string as well as the initial driver targets the A33.
Naming the registers as such would be more consistent.

Otherwise,

Reviewed-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>

Re: [linux-sunxi] [PATCH v3 2/5] iio: adc: sun4i-gpadc-iio: rename A23/A33-specified registers to contain A23

[icenowy-h8G6r0blFSE]

在 2017-07-24 14:02，Chen-Yu Tsai 写道：
> On Sun, Jul 23, 2017 at 10:13 PM, Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org> 
> wrote:
>> As the H3 SoC, which is also in sun8i line, has totally different
>> register map for the thermal sensor (a cut down version of GPADC), we
>> should rename A23/A33-specified registers to contain A23, in order to
>> prevent obfuscation with H3 registers. Currently these registers are
>> only prefixed "SUN8I", not "SUN8I_A23".
>> 
>> Add "_A23" after "SUN8I" on the register names.
> 
> Nit: the compatible string as well as the initial driver targets the 
> A33.
> Naming the registers as such would be more consistent.

But the registers are the same between A23 and A33.

In fact the only difference between A23 and A33 is the formula's 
factors.

> 
> Otherwise,
> 
> Reviewed-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
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Re: [PATCH v3 2/5] iio: adc: sun4i-gpadc-iio: rename A23/A33-specified registers to contain A23

[Chen-Yu Tsai]

On Mon, Jul 24, 2017 at 2:06 PM,  <icenowy-h8G6r0blFSE@public.gmane.org> wrote:
> 在 2017-07-24 14:02，Chen-Yu Tsai 写道：
>>
>> On Sun, Jul 23, 2017 at 10:13 PM, Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org> wrote:
>>>
>>> As the H3 SoC, which is also in sun8i line, has totally different
>>> register map for the thermal sensor (a cut down version of GPADC), we
>>> should rename A23/A33-specified registers to contain A23, in order to
>>> prevent obfuscation with H3 registers. Currently these registers are
>>> only prefixed "SUN8I", not "SUN8I_A23".
>>>
>>> Add "_A23" after "SUN8I" on the register names.
>>
>>
>> Nit: the compatible string as well as the initial driver targets the A33.
>> Naming the registers as such would be more consistent.
>
>
> But the registers are the same between A23 and A33.
>
> In fact the only difference between A23 and A33 is the formula's factors.

The goal here is to keep things consistent. Nothing in this driver as
it currently is mentions A23. Unless you plan on adding additional
commits to support the A23, and a note explaining the similarity
of the A23 and A33 ADCs, this is only going to confuse people.

ChenYu

>
>>
>> Otherwise,
>>
>> Reviewed-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
>
>
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[PATCH v3 4/5] ARM: sun8i: h3: add support for the thermal sensor in H3

[Icenowy Zheng]

As we have gained the support for the thermal sensor in H3, we can now
add its device nodes to the device tree.

Add them to the H3 device tree.

The H5 thermal sensor has some differences, and will be added furtherly.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
Changes in v3:
- Clock name changes.
- Splited out thermal zone addition.

 arch/arm/boot/dts/sun8i-h3.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index a0cee17fe44b..efe3a8e4f2af 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -108,6 +108,23 @@
 		};
 	};
 
+	iio-hwmon {
+		compatible = "iio-hwmon";
+		io-channels = <&ths>;
+	};
+
+	soc {
+		ths: thermal-sensor@1c25000 {
+			compatible = "allwinner,sun8i-h3-ths";
+			reg = <0x01c25000 0x100>;
+			clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
+			clock-names = "bus", "mod";
+			resets = <&ccu RST_BUS_THS>;
+			#thermal-sensor-cells = <0>;
+			#io-channel-cells = <0>;
+		};
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-- 
2.13.0

Re: [PATCH v3 4/5] ARM: sun8i: h3: add support for the thermal sensor in H3

[Chen-Yu Tsai]

On Sun, Jul 23, 2017 at 10:13 PM, Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org> wrote:
> As we have gained the support for the thermal sensor in H3, we can now
> add its device nodes to the device tree.
>
> Add them to the H3 device tree.
>
> The H5 thermal sensor has some differences, and will be added furtherly.
>
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>

Other than the possibility of referencing e-fuses for calibration data,
this patch looks good.

Reviewed-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>

[PATCH v3 1/5] dt-bindings: update the Allwinner GPADC device tree binding for H3

[Icenowy Zheng]

Allwinner H3 features a thermal sensor like the one in A33, but has its
register re-arranged, the clock divider moved to CCU (originally the
clock divider is in ADC) and added a pair of bus clock and reset.

Update the binding document to cover H3.

Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
Changes in v3:
- Clock name changes.
- Example node name changes.
- Add interupts (not yet used by the driver).

 .../devicetree/bindings/mfd/sun4i-gpadc.txt        | 25 ++++++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
index badff3611a98..986265c59b2a 100644
--- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
+++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
@@ -4,12 +4,21 @@ The Allwinner SoCs all have an ADC that can also act as a thermal sensor
 and sometimes as a touchscreen controller.
 
 Required properties:
-  - compatible: "allwinner,sun8i-a33-ths",
+  - compatible: must contain one of the following compatibles:
+		- "allwinner,sun8i-a33-ths"
+		- "allwinner,sun8i-h3-ths"
   - reg: mmio address range of the chip,
   - #thermal-sensor-cells: shall be 0,
   - #io-channel-cells: shall be 0,
 
-Example:
+Required properties for the following compatibles:
+		- "allwinner,sun8i-h3-ths"
+  - clocks: the bus clock and the input clock of the ADC,
+  - clock-names: should be "bus" and "mod",
+  - resets: the bus reset of the ADC,
+  - interrupts: the sampling interrupt of the ADC,
+
+Example for A33:
 	ths: ths@01c25000 {
 		compatible = "allwinner,sun8i-a33-ths";
 		reg = <0x01c25000 0x100>;
@@ -17,6 +26,18 @@ Example:
 		#io-channel-cells = <0>;
 	};
 
+Example for H3:
+	ths: thermal-sensor@1c25000 {
+		compatible = "allwinner,sun8i-h3-ths";
+		reg = <0x01c25000 0x400>;
+		clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
+		clock-names = "bus", "mod";
+		resets = <&ccu RST_BUS_THS>;
+		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+		#thermal-sensor-cells = <0>;
+		#io-channel-cells = <0>;
+	};
+
 sun4i, sun5i and sun6i SoCs are also supported via the older binding:
 
 sun4i resistive touchscreen controller
-- 
2.13.0

Re: [linux-sunxi] [PATCH v3 1/5] dt-bindings: update the Allwinner GPADC device tree binding for H3

[Chen-Yu Tsai]

On Sun, Jul 23, 2017 at 10:13 PM, Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org> wrote:
> Allwinner H3 features a thermal sensor like the one in A33, but has its
> register re-arranged, the clock divider moved to CCU (originally the
> clock divider is in ADC) and added a pair of bus clock and reset.
>
> Update the binding document to cover H3.
>
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>

Reviewed-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>

Re: [linux-sunxi] [PATCH v3 1/5] dt-bindings: update the Allwinner GPADC device tree binding for H3

[Chen-Yu Tsai]

On Mon, Jul 24, 2017 at 2:01 PM, Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> wrote:
> On Sun, Jul 23, 2017 at 10:13 PM, Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org> wrote:
>> Allwinner H3 features a thermal sensor like the one in A33, but has its
>> register re-arranged, the clock divider moved to CCU (originally the
>> clock divider is in ADC) and added a pair of bus clock and reset.
>>
>> Update the binding document to cover H3.
>>
>> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
>
> Reviewed-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>

One other thing. IIRC the new SoCs have ADC calibration data stored
somewhere in the e-fuses. Any chance you would use them, and need to
reference them in the device node?

ChenYu
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Re: [PATCH v3 1/5] dt-bindings: update the Allwinner GPADC device tree binding for H3

[Rob Herring]

On Sun, Jul 23, 2017 at 10:13:50PM +0800, Icenowy Zheng wrote:
> Allwinner H3 features a thermal sensor like the one in A33, but has its
> register re-arranged, the clock divider moved to CCU (originally the
> clock divider is in ADC) and added a pair of bus clock and reset.
> 
> Update the binding document to cover H3.
> 
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
> ---
> Changes in v3:
> - Clock name changes.
> - Example node name changes.
> - Add interupts (not yet used by the driver).
> 
>  .../devicetree/bindings/mfd/sun4i-gpadc.txt        | 25 ++++++++++++++++++++--
>  1 file changed, 23 insertions(+), 2 deletions(-)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

Re: [PATCH v3 1/5] dt-bindings: update the Allwinner GPADC device tree binding for H3

[Lee Jones]

On Sun, 23 Jul 2017, Icenowy Zheng wrote:

> Allwinner H3 features a thermal sensor like the one in A33, but has its
> register re-arranged, the clock divider moved to CCU (originally the
> clock divider is in ADC) and added a pair of bus clock and reset.
> 
> Update the binding document to cover H3.
> 
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
> ---
> Changes in v3:
> - Clock name changes.
> - Example node name changes.
> - Add interupts (not yet used by the driver).
> 
>  .../devicetree/bindings/mfd/sun4i-gpadc.txt        | 25 ++++++++++++++++++++--
>  1 file changed, 23 insertions(+), 2 deletions(-)

For my own reference:
  Acked-for-MFD-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

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Re: [PATCH v3 1/5] dt-bindings: update the Allwinner GPADC device tree binding for H3

[Vincent Legoll]

Hello,

Sorry for the very-clueless question

On Sun, Jul 23, 2017 at 4:13 PM, Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org> wrote:
> +  - clock-names: should be "bus" and "mod",

When I first read that, I wondered what value clock-names should
eally be given.

Then...

> +               clock-names = "bus", "mod";

OK, now this is clearer, but still the documentation is less documenting
than the code itself, sigh...

I cannot think of a better wording, though, as a non-native-english
speaker. Maybe just add a "(See example below)" would be
sufficient...

Or decide that this documentation is for clueful ones.

WDYT ?

-- 
Vincent Legoll

[PATCH v3 3/5] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor

[Icenowy Zheng]

This adds support for the Allwinner H3 thermal sensor.

Allwinner H3 has a thermal sensor like the one in A33, but have its
registers nearly all re-arranged, sample clock moved to CCU and a pair
of bus clock and reset added. It's also the base of newer SoCs' thermal
sensors.

Some new options is added to gpadc_data struct, to mark the difference
between the old GPADCs and THS's and the new THS's.

Thermal sampling via interrupts are still not supported, and polling
is used instead.

The thermal sensors on A64 and H5 is like the one on H3, but with of
course different formula factors.

Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
Changes in v3:
- Clock name changes.
- Fixed some small issues pointed out by Quentin.

 drivers/iio/adc/sun4i-gpadc-iio.c | 228 +++++++++++++++++++++++++++++++-------
 include/linux/mfd/sun4i-gpadc.h   |  27 +++++
 2 files changed, 215 insertions(+), 40 deletions(-)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c
index 41769bc6a429..5c79ba4d5ef5 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -22,6 +22,7 @@
  * shutdown for not being used.
  */
 
+#include <linux/clk.h>
 #include <linux/completion.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
@@ -31,6 +32,7 @@
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 #include <linux/regmap.h>
+#include <linux/reset.h>
 #include <linux/thermal.h>
 #include <linux/delay.h>
 
@@ -49,6 +51,8 @@ static unsigned int sun6i_gpadc_chan_select(unsigned int chan)
 	return SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(chan);
 }
 
+struct sun4i_gpadc_iio;
+
 struct gpadc_data {
 	int		temp_offset;
 	int		temp_scale;
@@ -56,39 +60,12 @@ struct gpadc_data {
 	unsigned int	tp_adc_select;
 	unsigned int	(*adc_chan_select)(unsigned int chan);
 	unsigned int	adc_chan_mask;
-};
-
-static const struct gpadc_data sun4i_gpadc_data = {
-	.temp_offset = -1932,
-	.temp_scale = 133,
-	.tp_mode_en = SUN4I_GPADC_CTRL1_TP_MODE_EN,
-	.tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
-	.adc_chan_select = &sun4i_gpadc_chan_select,
-	.adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
-};
-
-static const struct gpadc_data sun5i_gpadc_data = {
-	.temp_offset = -1447,
-	.temp_scale = 100,
-	.tp_mode_en = SUN4I_GPADC_CTRL1_TP_MODE_EN,
-	.tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
-	.adc_chan_select = &sun4i_gpadc_chan_select,
-	.adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
-};
-
-static const struct gpadc_data sun6i_gpadc_data = {
-	.temp_offset = -1623,
-	.temp_scale = 167,
-	.tp_mode_en = SUN6I_GPADC_CTRL1_TP_MODE_EN,
-	.tp_adc_select = SUN6I_GPADC_CTRL1_TP_ADC_SELECT,
-	.adc_chan_select = &sun6i_gpadc_chan_select,
-	.adc_chan_mask = SUN6I_GPADC_CTRL1_ADC_CHAN_MASK,
-};
-
-static const struct gpadc_data sun8i_a33_gpadc_data = {
-	.temp_offset = -1662,
-	.temp_scale = 162,
-	.tp_mode_en = SUN8I_A23_GPADC_CTRL1_CHOP_TEMP_EN,
+	unsigned int	temp_data;
+	int		(*sample_start)(struct sun4i_gpadc_iio *info);
+	int		(*sample_end)(struct sun4i_gpadc_iio *info);
+	bool		has_bus_clk;
+	bool		has_bus_rst;
+	bool		has_mod_clk;
 };
 
 struct sun4i_gpadc_iio {
@@ -103,6 +80,9 @@ struct sun4i_gpadc_iio {
 	atomic_t			ignore_temp_data_irq;
 	const struct gpadc_data		*data;
 	bool				no_irq;
+	struct clk			*ths_bus_clk;
+	struct clk			*mod_clk;
+	struct reset_control		*reset;
 	/* prevents concurrent reads of temperature and ADC */
 	struct mutex			mutex;
 	struct thermal_zone_device	*tzd;
@@ -276,7 +256,7 @@ static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val)
 	if (info->no_irq) {
 		pm_runtime_get_sync(indio_dev->dev.parent);
 
-		regmap_read(info->regmap, SUN4I_GPADC_TEMP_DATA, val);
+		regmap_read(info->regmap, info->data->temp_data, val);
 
 		pm_runtime_mark_last_busy(indio_dev->dev.parent);
 		pm_runtime_put_autosuspend(indio_dev->dev.parent);
@@ -384,10 +364,8 @@ static irqreturn_t sun4i_gpadc_fifo_data_irq_handler(int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
-static int sun4i_gpadc_runtime_suspend(struct device *dev)
+static int sun4i_gpadc_sample_end(struct sun4i_gpadc_iio *info)
 {
-	struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
-
 	/* Disable the ADC on IP */
 	regmap_write(info->regmap, SUN4I_GPADC_CTRL1, 0);
 	/* Disable temperature sensor on IP */
@@ -396,10 +374,23 @@ static int sun4i_gpadc_runtime_suspend(struct device *dev)
 	return 0;
 }
 
-static int sun4i_gpadc_runtime_resume(struct device *dev)
+static int sun8i_h3_gpadc_sample_end(struct sun4i_gpadc_iio *info)
+{
+	/* Disable temperature sensor */
+	regmap_write(info->regmap, SUN8I_H3_GPADC_CTRL2, 0);
+
+	return 0;
+}
+
+static int sun4i_gpadc_runtime_suspend(struct device *dev)
 {
 	struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
 
+	return info->data->sample_end(info);
+}
+
+static int sun4i_gpadc_sample_start(struct sun4i_gpadc_iio *info)
+{
 	/* clkin = 6MHz */
 	regmap_write(info->regmap, SUN4I_GPADC_CTRL0,
 		     SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(2) |
@@ -417,6 +408,29 @@ static int sun4i_gpadc_runtime_resume(struct device *dev)
 	return 0;
 }
 
+static int sun8i_h3_gpadc_sample_start(struct sun4i_gpadc_iio *info)
+{
+	regmap_write(info->regmap, SUN8I_H3_GPADC_CTRL2,
+		     SUN8I_H3_GPADC_CTRL2_TEMP_SENSE_EN |
+		     SUN8I_H3_GPADC_CTRL2_T_ACQ1(31));
+	regmap_write(info->regmap, SUN4I_GPADC_CTRL0,
+		     SUN4I_GPADC_CTRL0_T_ACQ(31));
+	regmap_write(info->regmap, SUN8I_H3_GPADC_CTRL3,
+		     SUN4I_GPADC_CTRL3_FILTER_EN |
+		     SUN4I_GPADC_CTRL3_FILTER_TYPE(1));
+	regmap_write(info->regmap, SUN8I_H3_GPADC_INTC,
+		     SUN8I_H3_GPADC_INTC_TEMP_PERIOD(800));
+
+	return 0;
+}
+
+static int sun4i_gpadc_runtime_resume(struct device *dev)
+{
+	struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
+
+	return info->data->sample_start(info);
+}
+
 static int sun4i_gpadc_get_temp(void *data, int *temp)
 {
 	struct sun4i_gpadc_iio *info = data;
@@ -491,11 +505,78 @@ static int sun4i_irq_init(struct platform_device *pdev, const char *name,
 	return 0;
 }
 
+static const struct gpadc_data sun4i_gpadc_data = {
+	.temp_offset = -1932,
+	.temp_scale = 133,
+	.tp_mode_en = SUN4I_GPADC_CTRL1_TP_MODE_EN,
+	.tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
+	.adc_chan_select = &sun4i_gpadc_chan_select,
+	.adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
+	.temp_data = SUN4I_GPADC_TEMP_DATA,
+	.sample_start = sun4i_gpadc_sample_start,
+	.sample_end = sun4i_gpadc_sample_end,
+};
+
+static const struct gpadc_data sun5i_gpadc_data = {
+	.temp_offset = -1447,
+	.temp_scale = 100,
+	.tp_mode_en = SUN4I_GPADC_CTRL1_TP_MODE_EN,
+	.tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
+	.adc_chan_select = &sun4i_gpadc_chan_select,
+	.adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
+	.temp_data = SUN4I_GPADC_TEMP_DATA,
+	.sample_start = sun4i_gpadc_sample_start,
+	.sample_end = sun4i_gpadc_sample_end,
+};
+
+static const struct gpadc_data sun6i_gpadc_data = {
+	.temp_offset = -1623,
+	.temp_scale = 167,
+	.tp_mode_en = SUN6I_GPADC_CTRL1_TP_MODE_EN,
+	.tp_adc_select = SUN6I_GPADC_CTRL1_TP_ADC_SELECT,
+	.adc_chan_select = &sun6i_gpadc_chan_select,
+	.adc_chan_mask = SUN6I_GPADC_CTRL1_ADC_CHAN_MASK,
+	.temp_data = SUN4I_GPADC_TEMP_DATA,
+	.sample_start = sun4i_gpadc_sample_start,
+	.sample_end = sun4i_gpadc_sample_end,
+};
+
+static const struct gpadc_data sun8i_a33_gpadc_data = {
+	.temp_offset = -1662,
+	.temp_scale = 162,
+	.tp_mode_en = SUN8I_A23_GPADC_CTRL1_CHOP_TEMP_EN,
+	.temp_data = SUN4I_GPADC_TEMP_DATA,
+	.sample_start = sun4i_gpadc_sample_start,
+	.sample_end = sun4i_gpadc_sample_end,
+};
+
+static const struct gpadc_data sun8i_h3_gpadc_data = {
+	/*
+	 * The original formula on the datasheet seems to be wrong.
+	 * These factors are calculated based on the formula in the BSP
+	 * kernel, which is originally Tem = 217 - (T / 8.253), in which Tem
+	 * is the temperature in Celsius degree and T is the raw value
+	 * from the sensor.
+	 */
+	.temp_offset = -1791,
+	.temp_scale = -121,
+	.temp_data = SUN8I_H3_GPADC_TEMP_DATA,
+	.sample_start = sun8i_h3_gpadc_sample_start,
+	.sample_end = sun8i_h3_gpadc_sample_end,
+	.has_bus_clk = true,
+	.has_bus_rst = true,
+	.has_mod_clk = true,
+};
+
 static const struct of_device_id sun4i_gpadc_of_id[] = {
 	{
 		.compatible = "allwinner,sun8i-a33-ths",
 		.data = &sun8i_a33_gpadc_data,
 	},
+	{
+		.compatible = "allwinner,sun8i-h3-ths",
+		.data = &sun8i_h3_gpadc_data,
+	},
 	{ /* sentinel */ }
 };
 
@@ -530,17 +611,75 @@ static int sun4i_gpadc_probe_dt(struct platform_device *pdev,
 		return ret;
 	}
 
+	if (info->data->has_bus_rst) {
+		info->reset = devm_reset_control_get(&pdev->dev, NULL);
+		if (IS_ERR(info->reset)) {
+			ret = PTR_ERR(info->reset);
+			return ret;
+		}
+
+		ret = reset_control_deassert(info->reset);
+		if (ret)
+			return ret;
+	}
+
+	if (info->data->has_bus_clk) {
+		info->ths_bus_clk = devm_clk_get(&pdev->dev, "bus");
+		if (IS_ERR(info->ths_bus_clk)) {
+			ret = PTR_ERR(info->ths_bus_clk);
+			goto assert_reset;
+		}
+
+		ret = clk_prepare_enable(info->ths_bus_clk);
+		if (ret)
+			goto assert_reset;
+	}
+
+	if (info->data->has_mod_clk) {
+		info->mod_clk = devm_clk_get(&pdev->dev, "mod");
+		if (IS_ERR(info->mod_clk)) {
+			ret = PTR_ERR(info->mod_clk);
+			goto disable_bus_clk;
+		}
+
+		/* Running at 6MHz */
+		ret = clk_set_rate(info->mod_clk, 6000000);
+		if (ret)
+			goto disable_bus_clk;
+
+		ret = clk_prepare_enable(info->mod_clk);
+		if (ret)
+			goto disable_bus_clk;
+	}
+
 	if (!IS_ENABLED(CONFIG_THERMAL_OF))
 		return 0;
 
 	info->sensor_device = &pdev->dev;
 	info->tzd = thermal_zone_of_sensor_register(info->sensor_device, 0,
 						    info, &sun4i_ts_tz_ops);
-	if (IS_ERR(info->tzd))
+	if (IS_ERR(info->tzd)) {
 		dev_err(&pdev->dev, "could not register thermal sensor: %ld\n",
 			PTR_ERR(info->tzd));
+		ret = PTR_ERR(info->tzd);
+		goto disable_mod_clk;
+	}
+
+	return 0;
+
+disable_mod_clk:
+	if (info->data->has_mod_clk)
+		clk_disable_unprepare(info->mod_clk);
+
+disable_bus_clk:
+	if (info->data->has_bus_clk)
+		clk_disable_unprepare(info->ths_bus_clk);
+
+assert_reset:
+	if (info->data->has_bus_rst)
+		reset_control_assert(info->reset);
 
-	return PTR_ERR_OR_ZERO(info->tzd);
+	return ret;
 }
 
 static int sun4i_gpadc_probe_mfd(struct platform_device *pdev,
@@ -699,6 +838,15 @@ static int sun4i_gpadc_remove(struct platform_device *pdev)
 	if (!info->no_irq)
 		iio_map_array_unregister(indio_dev);
 
+	if (info->data->has_mod_clk)
+		clk_disable_unprepare(info->mod_clk);
+
+	if (info->data->has_bus_clk)
+		clk_disable_unprepare(info->ths_bus_clk);
+
+	if (info->data->has_bus_rst)
+		reset_control_assert(info->reset);
+
 	return 0;
 }
 
diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h
index d31d962bb7d8..f794a2988a93 100644
--- a/include/linux/mfd/sun4i-gpadc.h
+++ b/include/linux/mfd/sun4i-gpadc.h
@@ -42,6 +42,9 @@
 #define SUN8I_A23_GPADC_CTRL1_CHOP_TEMP_EN		BIT(8)
 #define SUN8I_A23_GPADC_CTRL1_GPADC_CALI_EN		BIT(7)
 
+/* TP_CTRL1 bits for SoCs after H3 */
+#define SUN8I_H3_GPADC_CTRL1_GPADC_CALI_EN		BIT(17)
+
 #define SUN4I_GPADC_CTRL2				0x08
 
 #define SUN4I_GPADC_CTRL2_TP_SENSITIVE_ADJUST(x)	((GENMASK(3, 0) & (x)) << 28)
@@ -49,7 +52,17 @@
 #define SUN4I_GPADC_CTRL2_PRE_MEA_EN			BIT(24)
 #define SUN4I_GPADC_CTRL2_PRE_MEA_THRE_CNT(x)		(GENMASK(23, 0) & (x))
 
+#define SUN8I_H3_GPADC_CTRL2				0x40
+
+#define SUN8I_H3_GPADC_CTRL2_TEMP_SENSE_EN		BIT(0)
+#define SUN8I_H3_GPADC_CTRL2_T_ACQ1(x)			((GENMASK(15, 0) * (x)) << 16)
+
 #define SUN4I_GPADC_CTRL3				0x0c
+/*
+ * This register is named "Average filter Control Register" in H3 Datasheet,
+ * but the register's definition is the same as the old CTRL3 register.
+ */
+#define SUN8I_H3_GPADC_CTRL3				0x70
 
 #define SUN4I_GPADC_CTRL3_FILTER_EN			BIT(2)
 #define SUN4I_GPADC_CTRL3_FILTER_TYPE(x)		(GENMASK(1, 0) & (x))
@@ -71,6 +84,13 @@
 #define SUN4I_GPADC_INT_FIFOC_TP_UP_IRQ_EN		BIT(1)
 #define SUN4I_GPADC_INT_FIFOC_TP_DOWN_IRQ_EN		BIT(0)
 
+#define SUN8I_H3_GPADC_INTC				0x44
+
+#define SUN8I_H3_GPADC_INTC_TEMP_PERIOD(x)		((GENMASK(19, 0) & (x)) << 12)
+#define SUN8I_H3_GPADC_INTC_TEMP_DATA			BIT(8)
+#define SUN8I_H3_GPADC_INTC_TEMP_SHUT			BIT(4)
+#define SUN8I_H3_GPADC_INTC_TEMP_ALARM			BIT(0)
+
 #define SUN4I_GPADC_INT_FIFOS				0x14
 
 #define SUN4I_GPADC_INT_FIFOS_TEMP_DATA_PENDING		BIT(18)
@@ -80,9 +100,16 @@
 #define SUN4I_GPADC_INT_FIFOS_TP_UP_PENDING		BIT(1)
 #define SUN4I_GPADC_INT_FIFOS_TP_DOWN_PENDING		BIT(0)
 
+#define SUN8I_H3_GPADC_INTS				0x44
+
+#define SUN8I_H3_GPADC_INTS_TEMP_DATA			BIT(8)
+#define SUN8I_H3_GPADC_INTS_TEMP_SHUT			BIT(4)
+#define SUN8I_H3_GPADC_INTS_TEMP_ALARM			BIT(0)
+
 #define SUN4I_GPADC_CDAT				0x1c
 #define SUN4I_GPADC_TEMP_DATA				0x20
 #define SUN4I_GPADC_DATA				0x24
+#define SUN8I_H3_GPADC_TEMP_DATA			0x80
 
 #define SUN4I_GPADC_IRQ_FIFO_DATA			0
 #define SUN4I_GPADC_IRQ_TEMP_DATA			1
-- 
2.13.0

Re: [PATCH v3 3/5] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor

[Jonathan Cameron]

On Sun, 23 Jul 2017 22:13:52 +0800
Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org> wrote:

> This adds support for the Allwinner H3 thermal sensor.
> 
> Allwinner H3 has a thermal sensor like the one in A33, but have its
> registers nearly all re-arranged, sample clock moved to CCU and a pair
> of bus clock and reset added. It's also the base of newer SoCs' thermal
> sensors.
> 
> Some new options is added to gpadc_data struct, to mark the difference
> between the old GPADCs and THS's and the new THS's.
> 
> Thermal sampling via interrupts are still not supported, and polling
> is used instead.
> 
> The thermal sensors on A64 and H5 is like the one on H3, but with of
> course different formula factors.
> 
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
Looks good to me. Just need to give Quentin time to look at it and
*fingers crossed* I should be able to pick up in a few days.

Jonathan 
> ---
> Changes in v3:
> - Clock name changes.
> - Fixed some small issues pointed out by Quentin.
> 
>  drivers/iio/adc/sun4i-gpadc-iio.c | 228 +++++++++++++++++++++++++++++++-------
>  include/linux/mfd/sun4i-gpadc.h   |  27 +++++
>  2 files changed, 215 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c
> index 41769bc6a429..5c79ba4d5ef5 100644
> --- a/drivers/iio/adc/sun4i-gpadc-iio.c
> +++ b/drivers/iio/adc/sun4i-gpadc-iio.c
> @@ -22,6 +22,7 @@
>   * shutdown for not being used.
>   */
>  
> +#include <linux/clk.h>
>  #include <linux/completion.h>
>  #include <linux/interrupt.h>
>  #include <linux/io.h>
> @@ -31,6 +32,7 @@
>  #include <linux/platform_device.h>
>  #include <linux/pm_runtime.h>
>  #include <linux/regmap.h>
> +#include <linux/reset.h>
>  #include <linux/thermal.h>
>  #include <linux/delay.h>
>  
> @@ -49,6 +51,8 @@ static unsigned int sun6i_gpadc_chan_select(unsigned int chan)
>  	return SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(chan);
>  }
>  
> +struct sun4i_gpadc_iio;
> +
>  struct gpadc_data {
>  	int		temp_offset;
>  	int		temp_scale;
> @@ -56,39 +60,12 @@ struct gpadc_data {
>  	unsigned int	tp_adc_select;
>  	unsigned int	(*adc_chan_select)(unsigned int chan);
>  	unsigned int	adc_chan_mask;
> -};
> -
> -static const struct gpadc_data sun4i_gpadc_data = {
> -	.temp_offset = -1932,
> -	.temp_scale = 133,
> -	.tp_mode_en = SUN4I_GPADC_CTRL1_TP_MODE_EN,
> -	.tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
> -	.adc_chan_select = &sun4i_gpadc_chan_select,
> -	.adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
> -};
> -
> -static const struct gpadc_data sun5i_gpadc_data = {
> -	.temp_offset = -1447,
> -	.temp_scale = 100,
> -	.tp_mode_en = SUN4I_GPADC_CTRL1_TP_MODE_EN,
> -	.tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
> -	.adc_chan_select = &sun4i_gpadc_chan_select,
> -	.adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
> -};
> -
> -static const struct gpadc_data sun6i_gpadc_data = {
> -	.temp_offset = -1623,
> -	.temp_scale = 167,
> -	.tp_mode_en = SUN6I_GPADC_CTRL1_TP_MODE_EN,
> -	.tp_adc_select = SUN6I_GPADC_CTRL1_TP_ADC_SELECT,
> -	.adc_chan_select = &sun6i_gpadc_chan_select,
> -	.adc_chan_mask = SUN6I_GPADC_CTRL1_ADC_CHAN_MASK,
> -};
> -
> -static const struct gpadc_data sun8i_a33_gpadc_data = {
> -	.temp_offset = -1662,
> -	.temp_scale = 162,
> -	.tp_mode_en = SUN8I_A23_GPADC_CTRL1_CHOP_TEMP_EN,
> +	unsigned int	temp_data;
> +	int		(*sample_start)(struct sun4i_gpadc_iio *info);
> +	int		(*sample_end)(struct sun4i_gpadc_iio *info);
> +	bool		has_bus_clk;
> +	bool		has_bus_rst;
> +	bool		has_mod_clk;
>  };
>  
>  struct sun4i_gpadc_iio {
> @@ -103,6 +80,9 @@ struct sun4i_gpadc_iio {
>  	atomic_t			ignore_temp_data_irq;
>  	const struct gpadc_data		*data;
>  	bool				no_irq;
> +	struct clk			*ths_bus_clk;
> +	struct clk			*mod_clk;
> +	struct reset_control		*reset;
>  	/* prevents concurrent reads of temperature and ADC */
>  	struct mutex			mutex;
>  	struct thermal_zone_device	*tzd;
> @@ -276,7 +256,7 @@ static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val)
>  	if (info->no_irq) {
>  		pm_runtime_get_sync(indio_dev->dev.parent);
>  
> -		regmap_read(info->regmap, SUN4I_GPADC_TEMP_DATA, val);
> +		regmap_read(info->regmap, info->data->temp_data, val);
>  
>  		pm_runtime_mark_last_busy(indio_dev->dev.parent);
>  		pm_runtime_put_autosuspend(indio_dev->dev.parent);
> @@ -384,10 +364,8 @@ static irqreturn_t sun4i_gpadc_fifo_data_irq_handler(int irq, void *dev_id)
>  	return IRQ_HANDLED;
>  }
>  
> -static int sun4i_gpadc_runtime_suspend(struct device *dev)
> +static int sun4i_gpadc_sample_end(struct sun4i_gpadc_iio *info)
>  {
> -	struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
> -
>  	/* Disable the ADC on IP */
>  	regmap_write(info->regmap, SUN4I_GPADC_CTRL1, 0);
>  	/* Disable temperature sensor on IP */
> @@ -396,10 +374,23 @@ static int sun4i_gpadc_runtime_suspend(struct device *dev)
>  	return 0;
>  }
>  
> -static int sun4i_gpadc_runtime_resume(struct device *dev)
> +static int sun8i_h3_gpadc_sample_end(struct sun4i_gpadc_iio *info)
> +{
> +	/* Disable temperature sensor */
> +	regmap_write(info->regmap, SUN8I_H3_GPADC_CTRL2, 0);
> +
> +	return 0;
> +}
> +
> +static int sun4i_gpadc_runtime_suspend(struct device *dev)
>  {
>  	struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
>  
> +	return info->data->sample_end(info);
> +}
> +
> +static int sun4i_gpadc_sample_start(struct sun4i_gpadc_iio *info)
> +{
>  	/* clkin = 6MHz */
>  	regmap_write(info->regmap, SUN4I_GPADC_CTRL0,
>  		     SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(2) |
> @@ -417,6 +408,29 @@ static int sun4i_gpadc_runtime_resume(struct device *dev)
>  	return 0;
>  }
>  
> +static int sun8i_h3_gpadc_sample_start(struct sun4i_gpadc_iio *info)
> +{
> +	regmap_write(info->regmap, SUN8I_H3_GPADC_CTRL2,
> +		     SUN8I_H3_GPADC_CTRL2_TEMP_SENSE_EN |
> +		     SUN8I_H3_GPADC_CTRL2_T_ACQ1(31));
> +	regmap_write(info->regmap, SUN4I_GPADC_CTRL0,
> +		     SUN4I_GPADC_CTRL0_T_ACQ(31));
> +	regmap_write(info->regmap, SUN8I_H3_GPADC_CTRL3,
> +		     SUN4I_GPADC_CTRL3_FILTER_EN |
> +		     SUN4I_GPADC_CTRL3_FILTER_TYPE(1));
> +	regmap_write(info->regmap, SUN8I_H3_GPADC_INTC,
> +		     SUN8I_H3_GPADC_INTC_TEMP_PERIOD(800));
> +
> +	return 0;
> +}
> +
> +static int sun4i_gpadc_runtime_resume(struct device *dev)
> +{
> +	struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
> +
> +	return info->data->sample_start(info);
> +}
> +
>  static int sun4i_gpadc_get_temp(void *data, int *temp)
>  {
>  	struct sun4i_gpadc_iio *info = data;
> @@ -491,11 +505,78 @@ static int sun4i_irq_init(struct platform_device *pdev, const char *name,
>  	return 0;
>  }
>  
> +static const struct gpadc_data sun4i_gpadc_data = {
> +	.temp_offset = -1932,
> +	.temp_scale = 133,
> +	.tp_mode_en = SUN4I_GPADC_CTRL1_TP_MODE_EN,
> +	.tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
> +	.adc_chan_select = &sun4i_gpadc_chan_select,
> +	.adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
> +	.temp_data = SUN4I_GPADC_TEMP_DATA,
> +	.sample_start = sun4i_gpadc_sample_start,
> +	.sample_end = sun4i_gpadc_sample_end,
> +};
> +
> +static const struct gpadc_data sun5i_gpadc_data = {
> +	.temp_offset = -1447,
> +	.temp_scale = 100,
> +	.tp_mode_en = SUN4I_GPADC_CTRL1_TP_MODE_EN,
> +	.tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
> +	.adc_chan_select = &sun4i_gpadc_chan_select,
> +	.adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
> +	.temp_data = SUN4I_GPADC_TEMP_DATA,
> +	.sample_start = sun4i_gpadc_sample_start,
> +	.sample_end = sun4i_gpadc_sample_end,
> +};
> +
> +static const struct gpadc_data sun6i_gpadc_data = {
> +	.temp_offset = -1623,
> +	.temp_scale = 167,
> +	.tp_mode_en = SUN6I_GPADC_CTRL1_TP_MODE_EN,
> +	.tp_adc_select = SUN6I_GPADC_CTRL1_TP_ADC_SELECT,
> +	.adc_chan_select = &sun6i_gpadc_chan_select,
> +	.adc_chan_mask = SUN6I_GPADC_CTRL1_ADC_CHAN_MASK,
> +	.temp_data = SUN4I_GPADC_TEMP_DATA,
> +	.sample_start = sun4i_gpadc_sample_start,
> +	.sample_end = sun4i_gpadc_sample_end,
> +};
> +
> +static const struct gpadc_data sun8i_a33_gpadc_data = {
> +	.temp_offset = -1662,
> +	.temp_scale = 162,
> +	.tp_mode_en = SUN8I_A23_GPADC_CTRL1_CHOP_TEMP_EN,
> +	.temp_data = SUN4I_GPADC_TEMP_DATA,
> +	.sample_start = sun4i_gpadc_sample_start,
> +	.sample_end = sun4i_gpadc_sample_end,
> +};
> +
> +static const struct gpadc_data sun8i_h3_gpadc_data = {
> +	/*
> +	 * The original formula on the datasheet seems to be wrong.
> +	 * These factors are calculated based on the formula in the BSP
> +	 * kernel, which is originally Tem = 217 - (T / 8.253), in which Tem
> +	 * is the temperature in Celsius degree and T is the raw value
> +	 * from the sensor.
> +	 */
> +	.temp_offset = -1791,
> +	.temp_scale = -121,
> +	.temp_data = SUN8I_H3_GPADC_TEMP_DATA,
> +	.sample_start = sun8i_h3_gpadc_sample_start,
> +	.sample_end = sun8i_h3_gpadc_sample_end,
> +	.has_bus_clk = true,
> +	.has_bus_rst = true,
> +	.has_mod_clk = true,
> +};
> +
>  static const struct of_device_id sun4i_gpadc_of_id[] = {
>  	{
>  		.compatible = "allwinner,sun8i-a33-ths",
>  		.data = &sun8i_a33_gpadc_data,
>  	},
> +	{
> +		.compatible = "allwinner,sun8i-h3-ths",
> +		.data = &sun8i_h3_gpadc_data,
> +	},
>  	{ /* sentinel */ }
>  };
>  
> @@ -530,17 +611,75 @@ static int sun4i_gpadc_probe_dt(struct platform_device *pdev,
>  		return ret;
>  	}
>  
> +	if (info->data->has_bus_rst) {
> +		info->reset = devm_reset_control_get(&pdev->dev, NULL);
> +		if (IS_ERR(info->reset)) {
> +			ret = PTR_ERR(info->reset);
> +			return ret;
> +		}
> +
> +		ret = reset_control_deassert(info->reset);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	if (info->data->has_bus_clk) {
> +		info->ths_bus_clk = devm_clk_get(&pdev->dev, "bus");
> +		if (IS_ERR(info->ths_bus_clk)) {
> +			ret = PTR_ERR(info->ths_bus_clk);
> +			goto assert_reset;
> +		}
> +
> +		ret = clk_prepare_enable(info->ths_bus_clk);
> +		if (ret)
> +			goto assert_reset;
> +	}
> +
> +	if (info->data->has_mod_clk) {
> +		info->mod_clk = devm_clk_get(&pdev->dev, "mod");
> +		if (IS_ERR(info->mod_clk)) {
> +			ret = PTR_ERR(info->mod_clk);
> +			goto disable_bus_clk;
> +		}
> +
> +		/* Running at 6MHz */
> +		ret = clk_set_rate(info->mod_clk, 6000000);
> +		if (ret)
> +			goto disable_bus_clk;
> +
> +		ret = clk_prepare_enable(info->mod_clk);
> +		if (ret)
> +			goto disable_bus_clk;
> +	}
> +
>  	if (!IS_ENABLED(CONFIG_THERMAL_OF))
>  		return 0;
>  
>  	info->sensor_device = &pdev->dev;
>  	info->tzd = thermal_zone_of_sensor_register(info->sensor_device, 0,
>  						    info, &sun4i_ts_tz_ops);
> -	if (IS_ERR(info->tzd))
> +	if (IS_ERR(info->tzd)) {
>  		dev_err(&pdev->dev, "could not register thermal sensor: %ld\n",
>  			PTR_ERR(info->tzd));
> +		ret = PTR_ERR(info->tzd);
> +		goto disable_mod_clk;
> +	}
> +
> +	return 0;
> +
> +disable_mod_clk:
> +	if (info->data->has_mod_clk)
> +		clk_disable_unprepare(info->mod_clk);
> +
> +disable_bus_clk:
> +	if (info->data->has_bus_clk)
> +		clk_disable_unprepare(info->ths_bus_clk);
> +
> +assert_reset:
> +	if (info->data->has_bus_rst)
> +		reset_control_assert(info->reset);
>  
> -	return PTR_ERR_OR_ZERO(info->tzd);
> +	return ret;
>  }
>  
>  static int sun4i_gpadc_probe_mfd(struct platform_device *pdev,
> @@ -699,6 +838,15 @@ static int sun4i_gpadc_remove(struct platform_device *pdev)
>  	if (!info->no_irq)
>  		iio_map_array_unregister(indio_dev);
>  
> +	if (info->data->has_mod_clk)
> +		clk_disable_unprepare(info->mod_clk);
> +
> +	if (info->data->has_bus_clk)
> +		clk_disable_unprepare(info->ths_bus_clk);
> +
> +	if (info->data->has_bus_rst)
> +		reset_control_assert(info->reset);
> +
>  	return 0;
>  }
>  
> diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h
> index d31d962bb7d8..f794a2988a93 100644
> --- a/include/linux/mfd/sun4i-gpadc.h
> +++ b/include/linux/mfd/sun4i-gpadc.h
> @@ -42,6 +42,9 @@
>  #define SUN8I_A23_GPADC_CTRL1_CHOP_TEMP_EN		BIT(8)
>  #define SUN8I_A23_GPADC_CTRL1_GPADC_CALI_EN		BIT(7)
>  
> +/* TP_CTRL1 bits for SoCs after H3 */
> +#define SUN8I_H3_GPADC_CTRL1_GPADC_CALI_EN		BIT(17)
> +
>  #define SUN4I_GPADC_CTRL2				0x08
>  
>  #define SUN4I_GPADC_CTRL2_TP_SENSITIVE_ADJUST(x)	((GENMASK(3, 0) & (x)) << 28)
> @@ -49,7 +52,17 @@
>  #define SUN4I_GPADC_CTRL2_PRE_MEA_EN			BIT(24)
>  #define SUN4I_GPADC_CTRL2_PRE_MEA_THRE_CNT(x)		(GENMASK(23, 0) & (x))
>  
> +#define SUN8I_H3_GPADC_CTRL2				0x40
> +
> +#define SUN8I_H3_GPADC_CTRL2_TEMP_SENSE_EN		BIT(0)
> +#define SUN8I_H3_GPADC_CTRL2_T_ACQ1(x)			((GENMASK(15, 0) * (x)) << 16)
> +
>  #define SUN4I_GPADC_CTRL3				0x0c
> +/*
> + * This register is named "Average filter Control Register" in H3 Datasheet,
> + * but the register's definition is the same as the old CTRL3 register.
> + */
> +#define SUN8I_H3_GPADC_CTRL3				0x70
>  
>  #define SUN4I_GPADC_CTRL3_FILTER_EN			BIT(2)
>  #define SUN4I_GPADC_CTRL3_FILTER_TYPE(x)		(GENMASK(1, 0) & (x))
> @@ -71,6 +84,13 @@
>  #define SUN4I_GPADC_INT_FIFOC_TP_UP_IRQ_EN		BIT(1)
>  #define SUN4I_GPADC_INT_FIFOC_TP_DOWN_IRQ_EN		BIT(0)
>  
> +#define SUN8I_H3_GPADC_INTC				0x44
> +
> +#define SUN8I_H3_GPADC_INTC_TEMP_PERIOD(x)		((GENMASK(19, 0) & (x)) << 12)
> +#define SUN8I_H3_GPADC_INTC_TEMP_DATA			BIT(8)
> +#define SUN8I_H3_GPADC_INTC_TEMP_SHUT			BIT(4)
> +#define SUN8I_H3_GPADC_INTC_TEMP_ALARM			BIT(0)
> +
>  #define SUN4I_GPADC_INT_FIFOS				0x14
>  
>  #define SUN4I_GPADC_INT_FIFOS_TEMP_DATA_PENDING		BIT(18)
> @@ -80,9 +100,16 @@
>  #define SUN4I_GPADC_INT_FIFOS_TP_UP_PENDING		BIT(1)
>  #define SUN4I_GPADC_INT_FIFOS_TP_DOWN_PENDING		BIT(0)
>  
> +#define SUN8I_H3_GPADC_INTS				0x44
> +
> +#define SUN8I_H3_GPADC_INTS_TEMP_DATA			BIT(8)
> +#define SUN8I_H3_GPADC_INTS_TEMP_SHUT			BIT(4)
> +#define SUN8I_H3_GPADC_INTS_TEMP_ALARM			BIT(0)
> +
>  #define SUN4I_GPADC_CDAT				0x1c
>  #define SUN4I_GPADC_TEMP_DATA				0x20
>  #define SUN4I_GPADC_DATA				0x24
> +#define SUN8I_H3_GPADC_TEMP_DATA			0x80
>  
>  #define SUN4I_GPADC_IRQ_FIFO_DATA			0
>  #define SUN4I_GPADC_IRQ_TEMP_DATA			1

Re: [PATCH v3 3/5] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1099 bytes --]

On Sun, Jul 23, 2017 at 10:13:52PM +0800, Icenowy Zheng wrote:
> This adds support for the Allwinner H3 thermal sensor.
> 
> Allwinner H3 has a thermal sensor like the one in A33, but have its
> registers nearly all re-arranged, sample clock moved to CCU and a pair
> of bus clock and reset added. It's also the base of newer SoCs' thermal
> sensors.
> 
> Some new options is added to gpadc_data struct, to mark the difference
> between the old GPADCs and THS's and the new THS's.
> 
> Thermal sampling via interrupts are still not supported, and polling
> is used instead.
> 
> The thermal sensors on A64 and H5 is like the one on H3, but with of
> course different formula factors.
> 
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>

Could you split it in half? One patch that would rework the existing
code, the other one adding the H3 support?

That's going to be much easier to review, bisect and revert if need be
that way.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH v3 3/5] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 2158 bytes --]

Hi Icenowy,

[auto build test WARNING on robh/for-next]
[also build test WARNING on v4.13-rc2 next-20170724]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Icenowy-Zheng/IIO-based-thermal-sensor-driver-for-Allwinner-H3-SoC/20170725-035642
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: tile-allmodconfig (attached as .config)
compiler: tilegx-linux-gcc (GCC) 4.6.2
reproduce:
        wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=tile 

All warnings (new ones prefixed by >>):

   drivers/iio/adc/sun4i-gpadc-iio.c: In function 'sun8i_h3_gpadc_sample_start':
>> drivers/iio/adc/sun4i-gpadc-iio.c:415:8: warning: large integer implicitly truncated to unsigned type [-Woverflow]

vim +415 drivers/iio/adc/sun4i-gpadc-iio.c

   410	
   411	static int sun8i_h3_gpadc_sample_start(struct sun4i_gpadc_iio *info)
   412	{
   413		regmap_write(info->regmap, SUN8I_H3_GPADC_CTRL2,
   414			     SUN8I_H3_GPADC_CTRL2_TEMP_SENSE_EN |
 > 415			     SUN8I_H3_GPADC_CTRL2_T_ACQ1(31));
   416		regmap_write(info->regmap, SUN4I_GPADC_CTRL0,
   417			     SUN4I_GPADC_CTRL0_T_ACQ(31));
   418		regmap_write(info->regmap, SUN8I_H3_GPADC_CTRL3,
   419			     SUN4I_GPADC_CTRL3_FILTER_EN |
   420			     SUN4I_GPADC_CTRL3_FILTER_TYPE(1));
   421		regmap_write(info->regmap, SUN8I_H3_GPADC_INTC,
   422			     SUN8I_H3_GPADC_INTC_TEMP_PERIOD(800));
   423	
   424		return 0;
   425	}
   426	

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Re: [PATCH v3 3/5] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 3035 bytes --]

Hi Icenowy,

[auto build test WARNING on robh/for-next]
[also build test WARNING on v4.13-rc2 next-20170724]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Icenowy-Zheng/IIO-based-thermal-sensor-driver-for-Allwinner-H3-SoC/20170725-035642
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: sparc64-allmodconfig (attached as .config)
compiler: sparc64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=sparc64 

All warnings (new ones prefixed by >>):

   In file included from include/linux/kernel.h:10:0,
                    from include/linux/clk.h:16,
                    from drivers/iio/adc/sun4i-gpadc-iio.c:25:
   drivers/iio/adc/sun4i-gpadc-iio.c: In function 'sun8i_h3_gpadc_sample_start':
   include/linux/bitops.h:6:19: warning: large integer implicitly truncated to unsigned type [-Woverflow]
    #define BIT(nr)   (1UL << (nr))
                      ^
>> include/linux/mfd/sun4i-gpadc.h:57:45: note: in expansion of macro 'BIT'
    #define SUN8I_H3_GPADC_CTRL2_TEMP_SENSE_EN  BIT(0)
                                                ^~~
>> drivers/iio/adc/sun4i-gpadc-iio.c:414:8: note: in expansion of macro 'SUN8I_H3_GPADC_CTRL2_TEMP_SENSE_EN'
           SUN8I_H3_GPADC_CTRL2_TEMP_SENSE_EN |
           ^
--
   In file included from include/linux/kernel.h:10:0,
                    from include/linux/clk.h:16,
                    from drivers/iio//adc/sun4i-gpadc-iio.c:25:
   drivers/iio//adc/sun4i-gpadc-iio.c: In function 'sun8i_h3_gpadc_sample_start':
   include/linux/bitops.h:6:19: warning: large integer implicitly truncated to unsigned type [-Woverflow]
    #define BIT(nr)   (1UL << (nr))
                      ^
>> include/linux/mfd/sun4i-gpadc.h:57:45: note: in expansion of macro 'BIT'
    #define SUN8I_H3_GPADC_CTRL2_TEMP_SENSE_EN  BIT(0)
                                                ^~~
   drivers/iio//adc/sun4i-gpadc-iio.c:414:8: note: in expansion of macro 'SUN8I_H3_GPADC_CTRL2_TEMP_SENSE_EN'
           SUN8I_H3_GPADC_CTRL2_TEMP_SENSE_EN |
           ^

vim +/BIT +57 include/linux/mfd/sun4i-gpadc.h

    56	
  > 57	#define SUN8I_H3_GPADC_CTRL2_TEMP_SENSE_EN		BIT(0)
    58	#define SUN8I_H3_GPADC_CTRL2_T_ACQ1(x)			((GENMASK(15, 0) * (x)) << 16)
    59	

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[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 51321 bytes --]

[PATCH v3 5/5] ARM: sun8i: h3: add partial CPU thermal zone

[Icenowy Zheng]

Because of the restriction of the OF thermal framework, the thermal
sensor will fail to probe if the thermal zone doesn't exist.

Add a partial thermal zone which claims the H3 THS as the thermal sensor.

The cooling device (CPU DVFS) is still not added as it's not ready, and
the trip points are also not added yet.

Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index efe3a8e4f2af..551efecaab5d 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -125,6 +125,15 @@
 		};
 	};
 
+	thermal-zones {
+		cpu-thermal {
+			/* milliseconds */
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+			thermal-sensors = <&ths>;
+		};
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-- 
2.13.0