From: Chen-Yu Tsai <wens@csie.org>
To: Icenowy Zheng <icenowy@aosc.io>
Cc: Chen-Yu Tsai <wens@csie.org>,
devicetree <devicetree@vger.kernel.org>,
"linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Maxime Ripard <maxime.ripard@free-electrons.com>,
linux-clk <linux-clk@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v3 08/10] clk: sunxi-ng: support R40 SoC
Date: Sat, 12 Aug 2017 13:16:00 +0800 [thread overview]
Message-ID: <CAGb2v65dwLGGnJrK4dDX2oFOPGMdGKbdrHidjjvHQxgfCcYrhQ@mail.gmail.com> (raw)
In-Reply-To: <36d3f8302887937ff18067fd6f6bc38d@aosc.io>
On Sat, Aug 12, 2017 at 12:51 PM, <icenowy@aosc.io> wrote:
> 在 2017-08-12 12:04,Chen-Yu Tsai 写道:
>>
>> On Sat, Jul 22, 2017 at 11:00 AM, <icenowy@aosc.io> wrote:
>>>
>>> 在 2017-05-29 15:34,Chen-Yu Tsai 写道:
>>>>
>>>>
>>>> Hi,
>>>>
>>>> On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote:
>>
>>
>> [...]
>>
>>>>> +
>>>>> +/*
>>>>> + * For the special bit in gate part, please see the BSP source code at
>>>>> + *
>>>>>
>>>>> https://github.com/BPI-SINOVOIP/BPI-M2U-bsp/blob/master/linux-sunxi/drivers/clk/sunxi/clk-sun8iw11.c#L665
>>>>> + */
>>>>> +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_sata_clk, "pll-sata",
>>>>> + "osc24M", 0x034,
>>>>> + 8, 5, /* N */
>>>>> + 4, 2, /* K */
>>>>> + 0, 2, /* M */
>>>>> + BIT(31) | BIT(14), /* gate */
>>>>> + BIT(28), /* lock */
>>>>> + 0);
>>>>
>>>>
>>>>
>>>> I think this is a somewhat simplified approach. From what I understand
>>>> of the user manual, the SATA clock path look like:
>>>>
>>>>
>>>> [ PLL-PERIPH0-SATA ] -\
>>>> mux @ 0x34 bit 30 --- gate @ 0x34 bit 14 --- ...
>>>> [ PLL-SATA ] ---------/
>>>>
>>>> ... from above ... ------\
>>>> mux @ 0xc8 bit 24 --- gate @ 0xc8 bit 31
>>>> [ external oscillator ] -/
>>>>
>>>> If you choose to simplify the implementation, please include a detailed
>>>> note as to why you chose to do so, and the validity of the
>>>> simplification.
>>>
>>>
>>>
>>> I think it can be fully implemented...
>>>
>>> But how should I call the internal clock controlled by the mux @ 0x34 bit
>>> 30?
>>
>>
>> sata-pll-mux?
>
>
> I choose to call it pll-sata-out, as the mux @ 0x34 bit 30 is called
> "PLL_OUTPUT_SEL".
Cool. Note that the clock names don't really matter for end users.
The only place this is visible is debugfs, or if some driver prints
it out for debug messages. So the only real requirement is that the
name makes some sense to any developers using it, in a way that they
can spot if they are using it wrong, like accidentally using a clock
for another module, and being able to roughly match it up to the
datasheet.
ChenYu
next prev parent reply other threads:[~2017-08-12 5:16 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-27 10:22 [PATCH v3 00/10] Initial Allwinner R40 support Icenowy Zheng
2017-05-27 10:22 ` [PATCH v3 01/10] arm: sunxi: add support for R40 SoC Icenowy Zheng
2017-05-28 14:57 ` Chen-Yu Tsai
2017-05-31 19:42 ` Rob Herring
2017-05-27 10:23 ` [PATCH v3 02/10] pinctrl: sunxi: Add SoC ID definitions for A10, A20 and R40 SoCs Icenowy Zheng
[not found] ` <20170527102308.1988-3-icenowy-h8G6r0blFSE@public.gmane.org>
2017-05-28 14:58 ` Chen-Yu Tsai
2017-05-29 16:33 ` Linus Walleij
2017-05-27 10:23 ` [PATCH v3 03/10] pinctrl: sunxi: add A20 support to A10 driver Icenowy Zheng
[not found] ` <20170527102308.1988-4-icenowy-h8G6r0blFSE@public.gmane.org>
2017-05-28 15:06 ` Chen-Yu Tsai
2017-05-29 16:35 ` Linus Walleij
2017-05-27 10:23 ` [PATCH v3 04/10] pinctrl: sunxi: drop dedicated A20 driver Icenowy Zheng
[not found] ` <20170527102308.1988-5-icenowy-h8G6r0blFSE@public.gmane.org>
2017-05-28 15:08 ` Chen-Yu Tsai
2017-05-29 16:39 ` Linus Walleij
2017-05-27 10:23 ` [PATCH v3 05/10] dt-bindings: add compatible string for Allwinner R40 pinctrl Icenowy Zheng
2017-05-28 15:09 ` Chen-Yu Tsai
[not found] ` <20170527102308.1988-6-icenowy-h8G6r0blFSE@public.gmane.org>
2017-05-29 16:40 ` Linus Walleij
2017-05-27 10:23 ` [PATCH v3 06/10] pinctrl: sunxi: add support of R40 to A10 pinctrl driver Icenowy Zheng
2017-05-29 13:11 ` Chen-Yu Tsai
[not found] ` <20170529131100.a56rv3e5z3kpcxuo-SLa5LZP+eSXNLxjTenLetw@public.gmane.org>
2017-05-29 13:19 ` icenowy-h8G6r0blFSE
2017-05-29 13:25 ` Chen-Yu Tsai
2017-05-29 16:43 ` Linus Walleij
[not found] ` <20170527102308.1988-1-icenowy-h8G6r0blFSE@public.gmane.org>
2017-05-27 10:23 ` [PATCH v3 07/10] dt-bindings: add compatible string for Allwinner R40 CCU Icenowy Zheng
2017-05-28 15:09 ` Chen-Yu Tsai
2017-08-19 8:17 ` Chen-Yu Tsai
2017-05-27 10:23 ` [PATCH v3 08/10] clk: sunxi-ng: support R40 SoC Icenowy Zheng
2017-05-29 7:34 ` Chen-Yu Tsai
2017-07-22 3:00 ` icenowy
2017-08-12 4:04 ` Chen-Yu Tsai
2017-08-12 4:51 ` icenowy
2017-08-12 5:16 ` Chen-Yu Tsai [this message]
2017-08-12 4:04 ` icenowy
2017-08-12 4:05 ` Chen-Yu Tsai
2017-05-27 10:23 ` [PATCH v3 09/10] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40 Icenowy Zheng
[not found] ` <20170527102308.1988-10-icenowy-h8G6r0blFSE@public.gmane.org>
2017-05-29 8:15 ` Chen-Yu Tsai
2017-05-27 10:23 ` [PATCH v3 10/10] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra Icenowy Zheng
2017-05-29 8:59 ` Chen-Yu Tsai
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