From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chen-Yu Tsai Subject: Re: Re: [RFC PATCH 01/11] dt-bindings: update the binding for Allwinner H3 TVE support Date: Sat, 20 May 2017 10:01:41 +0800 Message-ID: References: <20170517164354.16399-1-icenowy@aosc.io> <20170517164354.16399-2-icenowy@aosc.io> <20170519180215.7lc7duueu74pt4kz@flea.home> Reply-To: wens-jdAy2FN1RRM@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Icenowy Zheng Cc: linux-arm-kernel , Maxime Ripard , devicetree , linux-sunxi , linux-kernel , dri-devel , Chen-Yu Tsai , Rob Herring , linux-clk List-Id: devicetree@vger.kernel.org On Sat, May 20, 2017 at 2:06 AM, Icenowy Zheng wrote: > > > =E4=BA=8E 2017=E5=B9=B45=E6=9C=8820=E6=97=A5 GMT+08:00 =E4=B8=8A=E5=8D=88= 2:02:15, Maxime Ripard =E5=86=99=E5=88= =B0: >>On Thu, May 18, 2017 at 12:43:44AM +0800, Icenowy Zheng wrote: >>> -On SoCs other than the A33 and V3s, there is one more clock >>required: >>> +For the following compatibles: >>> + * allwinner,sun5i-a13-tcon >>> + * allwinner,sun6i-a31-tcon >>> + * allwinner,sun6i-a31s-tcon >>> + * allwinner,sun8i-a33-tcon >>> + * allwinner,sun8i-v3s-tcon >>> +there is one more clock and one more property required: >>> + - clocks: >>> + - 'tcon-ch0': The clock driving the TCON channel 0 >>> + - clock-output-names: Name of the pixel clock created >>> + >>> +For the following compatibles: >>> + * allwinner,sun5i-a13-tcon >>> + * allwinner,sun6i-a31-tcon >>> + * allwinner,sun6i-a31s-tcon >>> + * allwinner,sun8i-h3-tcon0 >>> +there is one more clock required: >>> - 'tcon-ch1': The clock driving the TCON channel 1 >> >>Putting ID's in the compatible name is usually a bad idea. What is the >>difference between the two? Only that the second one doesn't have a >>clock? > > Yes. > >> >>That seems highly unlikely. How does it generate the pixel clock >>frequency? > > Yes it seems impossible, but it's also the fact. > > There's only one CLK_TCON in H3/5, which is for TCON0. > > It's possible that lcd-ch1 clk is CLK_TVE, but it's still a weird situati= on -- > Although we have a lcd-ch1 clock, we cannot touch it, otherwise > the TVE will refuse to work (the TVE can only work under 216MHz). Assuming the TV encoder is like the old one, then it never had a separate module clock. Instead its timing signals are fed from the TCON. So CLK_TVE is likely the clock for TCON1 here. ChenYu --=20 You received this message because you are subscribed to the Google Groups "= linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an e= mail to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout.