* [PATCH 1/8] dt-bindings: phy: sun4i-usb-phy: Add property descriptions for H3
[not found] ` <20170803081411.22389-1-wens-jdAy2FN1RRM@public.gmane.org>
@ 2017-08-03 8:14 ` Chen-Yu Tsai
[not found] ` <20170803081411.22389-2-wens-jdAy2FN1RRM@public.gmane.org>
2017-08-03 8:14 ` [PATCH 2/8] dt-bindings: phy: sun4i-usb-phy: Add compatible string for A83T Chen-Yu Tsai
` (7 subsequent siblings)
8 siblings, 1 reply; 16+ messages in thread
From: Chen-Yu Tsai @ 2017-08-03 8:14 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Maxime Ripard, Rob Herring, Mark Rutland
Cc: Chen-Yu Tsai, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
The Allwinner H3 SoC has 4 USB PHYs, so it needs four sets of pmu
regions, clocks, resets, and optional vbus properties. These were
not described when the H3 compatible string was added.
Fixes: 626a630e003c ("phy-sun4i-usb: Add support for the host usb-phys
found on the H3 SoC")
Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---
Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index 005bc22938ff..893dd01dfe64 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -17,18 +17,21 @@ Required properties:
* "phy_ctrl"
* "pmu0" for H3, V3s and A64
* "pmu1"
- * "pmu2" for sun4i, sun6i or sun7i
+ * "pmu2" for sun4i, sun6i, sun7i or sun8i-h3
+ * "pmu3" for sun8i-h3
- #phy-cells : from the generic phy bindings, must be 1
- clocks : phandle + clock specifier for the phy clocks
- clock-names :
* "usb_phy" for sun4i, sun5i or sun7i
* "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i
* "usb0_phy", "usb1_phy" for sun8i
+ * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3
- resets : a list of phandle + reset specifier pairs
- reset-names :
* "usb0_reset"
* "usb1_reset"
- * "usb2_reset" for sun4i, sun6i or sun7i
+ * "usb2_reset" for sun4i, sun6i, sun7i or sun8i-h3
+ * "usb3_reset" for sun8i-h3
Optional properties:
- usb0_id_det-gpios : gpio phandle for reading the otg id pin value
@@ -37,6 +40,7 @@ Optional properties:
- usb0_vbus-supply : regulator phandle for controller usb0 vbus
- usb1_vbus-supply : regulator phandle for controller usb1 vbus
- usb2_vbus-supply : regulator phandle for controller usb2 vbus
+- usb3_vbus-supply : regulator phandle for controller usb3 vbus
Example:
usbphy: phy@0x01c13400 {
--
2.13.3
--
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 2/8] dt-bindings: phy: sun4i-usb-phy: Add compatible string for A83T
[not found] ` <20170803081411.22389-1-wens-jdAy2FN1RRM@public.gmane.org>
2017-08-03 8:14 ` [PATCH 1/8] dt-bindings: phy: sun4i-usb-phy: Add property descriptions for H3 Chen-Yu Tsai
@ 2017-08-03 8:14 ` Chen-Yu Tsai
[not found] ` <20170803081411.22389-3-wens-jdAy2FN1RRM@public.gmane.org>
2017-08-03 8:14 ` [PATCH 3/8] phy: sun4i-usb: Support secondary clock for HSIC PHY Chen-Yu Tsai
` (6 subsequent siblings)
8 siblings, 1 reply; 16+ messages in thread
From: Chen-Yu Tsai @ 2017-08-03 8:14 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Maxime Ripard, Rob Herring, Mark Rutland
Cc: Chen-Yu Tsai, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
The A83T has 3 USB PHYs, 1 for OTG, 1 for standard USB, 1 for USB HSIC.
Add a compatible string for it, and describe the needed properties.
Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
Tested-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index 893dd01dfe64..cbc7847dbf6c 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -9,6 +9,7 @@ Required properties:
* allwinner,sun7i-a20-usb-phy
* allwinner,sun8i-a23-usb-phy
* allwinner,sun8i-a33-usb-phy
+ * allwinner,sun8i-a83t-usb-phy
* allwinner,sun8i-h3-usb-phy
* allwinner,sun8i-v3s-usb-phy
* allwinner,sun50i-a64-usb-phy
@@ -17,7 +18,7 @@ Required properties:
* "phy_ctrl"
* "pmu0" for H3, V3s and A64
* "pmu1"
- * "pmu2" for sun4i, sun6i, sun7i or sun8i-h3
+ * "pmu2" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
* "pmu3" for sun8i-h3
- #phy-cells : from the generic phy bindings, must be 1
- clocks : phandle + clock specifier for the phy clocks
@@ -25,12 +26,13 @@ Required properties:
* "usb_phy" for sun4i, sun5i or sun7i
* "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i
* "usb0_phy", "usb1_phy" for sun8i
+ * "usb0_phy", "usb1_phy", "usb2_phy" and "usb2_hsic_12M" for sun8i-a83t
* "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3
- resets : a list of phandle + reset specifier pairs
- reset-names :
* "usb0_reset"
* "usb1_reset"
- * "usb2_reset" for sun4i, sun6i, sun7i or sun8i-h3
+ * "usb2_reset" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
* "usb3_reset" for sun8i-h3
Optional properties:
--
2.13.3
--
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 3/8] phy: sun4i-usb: Support secondary clock for HSIC PHY
[not found] ` <20170803081411.22389-1-wens-jdAy2FN1RRM@public.gmane.org>
2017-08-03 8:14 ` [PATCH 1/8] dt-bindings: phy: sun4i-usb-phy: Add property descriptions for H3 Chen-Yu Tsai
2017-08-03 8:14 ` [PATCH 2/8] dt-bindings: phy: sun4i-usb-phy: Add compatible string for A83T Chen-Yu Tsai
@ 2017-08-03 8:14 ` Chen-Yu Tsai
2017-08-03 8:14 ` [PATCH 4/8] phy: sun4i-usb: Support A83T USB PHYs Chen-Yu Tsai
` (5 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Chen-Yu Tsai @ 2017-08-03 8:14 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Maxime Ripard, Rob Herring, Mark Rutland
Cc: Chen-Yu Tsai, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
On the Allwinner A83T SoC, the last USB PHY is an HSIC PHY. It requires
two clocks instead of one.
On all Allwinner SoCs that share the common USB PHY design supported by
the phy-sun4i-usb driver, the first PHY is always tied to OTG, and there
is at most one HSIC PHY, typically the last.
In this patch we take advantage of these known constraints and store an
index in the compatible-string-related config structure describing which
PHY is HSIC, needing the extra hsic_12M clock.
Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index bbf06cfe5898..79157eced75a 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -107,6 +107,7 @@ enum sun4i_usb_phy_type {
struct sun4i_usb_phy_cfg {
int num_phys;
+ int hsic_index;
enum sun4i_usb_phy_type type;
u32 disc_thresh;
u8 phyctl_offset;
@@ -126,6 +127,7 @@ struct sun4i_usb_phy_data {
struct regulator *vbus;
struct reset_control *reset;
struct clk *clk;
+ struct clk *clk2;
bool regulator_on;
int index;
} phys[MAX_PHYS];
@@ -261,8 +263,15 @@ static int sun4i_usb_phy_init(struct phy *_phy)
if (ret)
return ret;
+ ret = clk_prepare_enable(phy->clk2);
+ if (ret) {
+ clk_disable_unprepare(phy->clk);
+ return ret;
+ }
+
ret = reset_control_deassert(phy->reset);
if (ret) {
+ clk_disable_unprepare(phy->clk2);
clk_disable_unprepare(phy->clk);
return ret;
}
@@ -315,6 +324,7 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
sun4i_usb_phy_passby(phy, 0);
reset_control_assert(phy->reset);
+ clk_disable_unprepare(phy->clk2);
clk_disable_unprepare(phy->clk);
return 0;
@@ -706,6 +716,17 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
return PTR_ERR(phy->clk);
}
+ /* The first PHY is always tied to OTG, and never HSIC */
+ if (data->cfg->hsic_index && i == data->cfg->hsic_index) {
+ /* HSIC needs secondary clock */
+ snprintf(name, sizeof(name), "usb%d_hsic_12M", i);
+ phy->clk2 = devm_clk_get(dev, name);
+ if (IS_ERR(phy->clk2)) {
+ dev_err(dev, "failed to get clock %s\n", name);
+ return PTR_ERR(phy->clk2);
+ }
+ }
+
snprintf(name, sizeof(name), "usb%d_reset", i);
phy->reset = devm_reset_control_get(dev, name);
if (IS_ERR(phy->reset)) {
--
2.13.3
--
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 4/8] phy: sun4i-usb: Support A83T USB PHYs
[not found] ` <20170803081411.22389-1-wens-jdAy2FN1RRM@public.gmane.org>
` (2 preceding siblings ...)
2017-08-03 8:14 ` [PATCH 3/8] phy: sun4i-usb: Support secondary clock for HSIC PHY Chen-Yu Tsai
@ 2017-08-03 8:14 ` Chen-Yu Tsai
2017-08-03 8:14 ` [PATCH 5/8] ARM: sun8i: a83t: Add USB PHY and host device nodes Chen-Yu Tsai
` (4 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Chen-Yu Tsai @ 2017-08-03 8:14 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Maxime Ripard, Rob Herring, Mark Rutland
Cc: Chen-Yu Tsai, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
The A83T has 3 USB PHYs, 1 for OTG, 1 for standard USB, 1 for USB HSIC.
The phy initialization procedure is very different from other SoCs, but
the PMU bits are the same, with additional bits for HSIC.
Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
Tested-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 66 ++++++++++++++++++++++++++++-------
1 file changed, 54 insertions(+), 12 deletions(-)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index 79157eced75a..af16f4fb9707 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -87,6 +87,16 @@
#define PHY_DISCON_TH_SEL 0x2a
#define PHY_SQUELCH_DETECT 0x3c
+/* A83T specific control bits for PHY0 */
+#define PHY_CTL_VBUSVLDEXT BIT(5)
+#define PHY_CTL_SIDDQ BIT(3)
+
+/* A83T specific control bits for PHY2 HSIC */
+#define SUNXI_EHCI_HS_FORCE BIT(20)
+#define SUNXI_HSIC_CONNECT_DET BIT(17)
+#define SUNXI_HSIC_CONNECT_INT BIT(16)
+#define SUNXI_HSIC BIT(1)
+
#define MAX_PHYS 4
/*
@@ -100,6 +110,7 @@ enum sun4i_usb_phy_type {
sun4i_a10_phy,
sun6i_a31_phy,
sun8i_a33_phy,
+ sun8i_a83t_phy,
sun8i_h3_phy,
sun8i_v3s_phy,
sun50i_a64_phy,
@@ -234,6 +245,7 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable)
{
+ struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
u32 bits, reg_value;
if (!phy->pmu)
@@ -242,6 +254,11 @@ static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable)
bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
+ /* A83T USB2 is HSIC */
+ if (phy_data->cfg->type == sun8i_a83t_phy && phy->index == 2)
+ bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
+ SUNXI_HSIC;
+
reg_value = readl(phy->pmu);
if (enable)
@@ -276,21 +293,30 @@ static int sun4i_usb_phy_init(struct phy *_phy)
return ret;
}
- if (phy->pmu && data->cfg->enable_pmu_unk1) {
- val = readl(phy->pmu + REG_PMU_UNK1);
- writel(val & ~2, phy->pmu + REG_PMU_UNK1);
- }
+ if (data->cfg->type == sun8i_a83t_phy) {
+ if (phy->index == 0) {
+ val = readl(data->base + data->cfg->phyctl_offset);
+ val |= PHY_CTL_VBUSVLDEXT;
+ val &= ~PHY_CTL_SIDDQ;
+ writel(val, data->base + data->cfg->phyctl_offset);
+ }
+ } else {
+ if (phy->pmu && data->cfg->enable_pmu_unk1) {
+ val = readl(phy->pmu + REG_PMU_UNK1);
+ writel(val & ~2, phy->pmu + REG_PMU_UNK1);
+ }
- /* Enable USB 45 Ohm resistor calibration */
- if (phy->index == 0)
- sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
+ /* Enable USB 45 Ohm resistor calibration */
+ if (phy->index == 0)
+ sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
- /* Adjust PHY's magnitude and rate */
- sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
+ /* Adjust PHY's magnitude and rate */
+ sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
- /* Disconnect threshold adjustment */
- sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
- data->cfg->disc_thresh, 2);
+ /* Disconnect threshold adjustment */
+ sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
+ data->cfg->disc_thresh, 2);
+ }
sun4i_usb_phy_passby(phy, 1);
@@ -316,6 +342,13 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
if (phy->index == 0) {
+ if (data->cfg->type == sun8i_a83t_phy) {
+ void __iomem *phyctl = data->base +
+ data->cfg->phyctl_offset;
+
+ writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
+ }
+
/* Disable pull-ups */
sun4i_usb_phy0_update_iscr(_phy, ISCR_DPDM_PULLUP_EN, 0);
sun4i_usb_phy0_update_iscr(_phy, ISCR_ID_PULLUP_EN, 0);
@@ -853,6 +886,14 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
.enable_pmu_unk1 = false,
};
+static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
+ .num_phys = 3,
+ .hsic_index = 2,
+ .type = sun8i_a83t_phy,
+ .phyctl_offset = REG_PHYCTL_A33,
+ .dedicated_clocks = true,
+};
+
static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
.num_phys = 4,
.type = sun8i_h3_phy,
@@ -889,6 +930,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = "allwinner,sun7i-a20-usb-phy", .data = &sun7i_a20_cfg },
{ .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg },
{ .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
+ { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = &sun8i_a83t_cfg },
{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = &sun8i_v3s_cfg },
{ .compatible = "allwinner,sun50i-a64-usb-phy",
--
2.13.3
--
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 5/8] ARM: sun8i: a83t: Add USB PHY and host device nodes
[not found] ` <20170803081411.22389-1-wens-jdAy2FN1RRM@public.gmane.org>
` (3 preceding siblings ...)
2017-08-03 8:14 ` [PATCH 4/8] phy: sun4i-usb: Support A83T USB PHYs Chen-Yu Tsai
@ 2017-08-03 8:14 ` Chen-Yu Tsai
2017-08-03 8:14 ` [PATCH 6/8] ARM: sun8i: a83t: Add device node for USB OTG controller Chen-Yu Tsai
` (3 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Chen-Yu Tsai @ 2017-08-03 8:14 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Maxime Ripard, Rob Herring, Mark Rutland
Cc: Chen-Yu Tsai, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
The A83T has 3 USB PHYs, 1 for USB OTG, 1 for standard USB 2.0, 1 for
USB HSIC. EHCI0/OHCI0 are the standard USB host pair, while EHCI1 is
the host controller for HSIC. OTG is not added yet.
Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
Tested-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 62 +++++++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 61304761e8f6..6039f1ea6810 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -242,6 +242,68 @@
#size-cells = <0>;
};
+ usbphy: phy@1c19400 {
+ compatible = "allwinner,sun8i-a83t-usb-phy";
+ reg = <0x01c19400 0x10>,
+ <0x01c1a800 0x14>,
+ <0x01c1b800 0x14>;
+ reg-names = "phy_ctrl",
+ "pmu1",
+ "pmu2";
+ clocks = <&ccu CLK_USB_PHY0>,
+ <&ccu CLK_USB_PHY1>,
+ <&ccu CLK_USB_HSIC>,
+ <&ccu CLK_USB_HSIC_12M>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy",
+ "usb2_hsic_12M";
+ resets = <&ccu RST_USB_PHY0>,
+ <&ccu RST_USB_PHY1>,
+ <&ccu RST_USB_HSIC>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci0: usb@1c1a000 {
+ compatible = "allwinner,sun8i-a83t-ehci",
+ "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI0>;
+ resets = <&ccu RST_BUS_EHCI0>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb@1c1a400 {
+ compatible = "allwinner,sun8i-a83t-ohci",
+ "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci1: usb@1c1b000 {
+ compatible = "allwinner,sun8i-a83t-ehci",
+ "generic-ehci";
+ reg = <0x01c1b000 0x100>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI1>;
+ resets = <&ccu RST_BUS_EHCI1>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-a83t-ccu";
reg = <0x01c20000 0x400>;
--
2.13.3
--
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^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 6/8] ARM: sun8i: a83t: Add device node for USB OTG controller
[not found] ` <20170803081411.22389-1-wens-jdAy2FN1RRM@public.gmane.org>
` (4 preceding siblings ...)
2017-08-03 8:14 ` [PATCH 5/8] ARM: sun8i: a83t: Add USB PHY and host device nodes Chen-Yu Tsai
@ 2017-08-03 8:14 ` Chen-Yu Tsai
2017-08-03 8:14 ` [PATCH 7/8] ARM: sun8i: a83t: cubietruck-plus: Enable onboard USB peripherals Chen-Yu Tsai
` (2 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Chen-Yu Tsai @ 2017-08-03 8:14 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Maxime Ripard, Rob Herring, Mark Rutland
Cc: Chen-Yu Tsai, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
The USB OTG controller found on the A83T is compatible with the one
found on the A33.
Add a device node for it.
Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 6039f1ea6810..f996bd343e50 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -242,6 +242,20 @@
#size-cells = <0>;
};
+ usb_otg: usb@01c19000 {
+ compatible = "allwinner,sun8i-a83t-musb",
+ "allwinner,sun8i-a33-musb";
+ reg = <0x01c19000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ status = "disabled";
+ };
+
usbphy: phy@1c19400 {
compatible = "allwinner,sun8i-a83t-usb-phy";
reg = <0x01c19400 0x10>,
--
2.13.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 7/8] ARM: sun8i: a83t: cubietruck-plus: Enable onboard USB peripherals
[not found] ` <20170803081411.22389-1-wens-jdAy2FN1RRM@public.gmane.org>
` (5 preceding siblings ...)
2017-08-03 8:14 ` [PATCH 6/8] ARM: sun8i: a83t: Add device node for USB OTG controller Chen-Yu Tsai
@ 2017-08-03 8:14 ` Chen-Yu Tsai
2017-08-03 8:14 ` [PATCH 8/8] ARM: sun8i: a83t: h8homlet-v2: Enable USB ports Chen-Yu Tsai
2017-08-19 2:41 ` [PATCH 0/8] ARM: sun8i: a83t: Add USB host support Chen-Yu Tsai
8 siblings, 0 replies; 16+ messages in thread
From: Chen-Yu Tsai @ 2017-08-03 8:14 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Maxime Ripard, Rob Herring, Mark Rutland
Cc: Chen-Yu Tsai, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
The Cubietruck-plus has a GL830 USB-to-SATA bridge connected to EHCI0,
and a USB3503 HSIC USB 2.0 hub connected to EHCI1. The USB3503's I2C
control interface is not connected.
This patch enables both EHCI controllers, adds a device node for the
USB hub, and includes sunxi-common-regulators.dtsi for the VBUS
regulators. The existing reg_vcc3v3 is dropped as it is also available
in the set of common regulators. Other unused regulators are disabled.
Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---
arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 49 +++++++++++++++++++++---
1 file changed, 44 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
index f583e5b9a1c8..716a205c6dbb 100644
--- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
@@ -44,6 +44,7 @@
/dts-v1/;
#include "sun8i-a83t.dtsi"
+#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
@@ -83,11 +84,15 @@
};
};
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
+ usb-hub {
+ /* I2C is not connected */
+ compatible = "smsc,usb3503";
+ initial-mode = <1>; /* initialize in HUB mode */
+ disabled-ports = <1>;
+ intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ reset-gpios = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */
+ connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
+ refclk-frequency = <19200000>;
};
sound {
@@ -109,6 +114,16 @@
};
};
+&ehci0 {
+ /* GL830 USB-to-SATA bridge here */
+ status = "okay";
+};
+
+&ehci1 {
+ /* USB3503 HSIC USB 2.0 hub here */
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
@@ -164,6 +179,24 @@
};
};
+®_usb1_vbus {
+ gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */
+ status = "okay";
+};
+
+®_usb2_vbus {
+ gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+ status = "okay";
+};
+
+®_vcc3v0 {
+ status = "disabled";
+};
+
+®_vcc5v0 {
+ status = "disabled";
+};
+
&spdif {
status = "okay";
};
@@ -173,3 +206,9 @@
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--
2.13.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 8/8] ARM: sun8i: a83t: h8homlet-v2: Enable USB ports
[not found] ` <20170803081411.22389-1-wens-jdAy2FN1RRM@public.gmane.org>
` (6 preceding siblings ...)
2017-08-03 8:14 ` [PATCH 7/8] ARM: sun8i: a83t: cubietruck-plus: Enable onboard USB peripherals Chen-Yu Tsai
@ 2017-08-03 8:14 ` Chen-Yu Tsai
2017-08-19 2:41 ` [PATCH 0/8] ARM: sun8i: a83t: Add USB host support Chen-Yu Tsai
8 siblings, 0 replies; 16+ messages in thread
From: Chen-Yu Tsai @ 2017-08-03 8:14 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Maxime Ripard, Rob Herring, Mark Rutland
Cc: Chen-Yu Tsai, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
The h8homlet board has the A83T's standard USB 1.1/2.0 host pair routed
to a USB host port on the board. The other USB host port is routed to
USB OTG controller.
Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---
.../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 29 ++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
index e0055180d29f..1f0d60afb25b 100644
--- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -58,6 +58,10 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
@@ -78,6 +82,20 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
+®_usb0_vbus {
+ gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
+ status = "okay";
+};
+
+®_usb1_vbus {
+ gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+ status = "okay";
+};
+
&r_rsb {
status = "okay";
@@ -118,3 +136,14 @@
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
+
+&usbphy {
+ usb0_vbus-supply = <®_usb0_vbus>;
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
--
2.13.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 0/8] ARM: sun8i: a83t: Add USB host support
[not found] ` <20170803081411.22389-1-wens-jdAy2FN1RRM@public.gmane.org>
` (7 preceding siblings ...)
2017-08-03 8:14 ` [PATCH 8/8] ARM: sun8i: a83t: h8homlet-v2: Enable USB ports Chen-Yu Tsai
@ 2017-08-19 2:41 ` Chen-Yu Tsai
8 siblings, 0 replies; 16+ messages in thread
From: Chen-Yu Tsai @ 2017-08-19 2:41 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Kishon Vijay Abraham I, Maxime Ripard, Rob Herring, Mark Rutland,
linux-arm-kernel, devicetree, linux-sunxi
On Thu, Aug 3, 2017 at 4:14 PM, Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> wrote:
> Hi everyone,
>
> This series enables USB host support for the Allwinner A83T SoC.
> The A83T's USB OTG PHY uses different controls. The USB 2.0 host
> PHYs are the same as previous chips. And the HSIC part is actually
> used on some boards.
>
> The external bits needed for proper USB OTG support is not there
> yet, namely the regulators and power supplies for VBUS sensing and
> control. This will be enabled later on. However the OTG controller
> is the same as the one found in previous chips. This has been tested
> under U-boot.
>
> Patch 1 adds some properties that were missing for the H3. The H3
> has 4 USB host controllers, so there are also 4 USB host PHYs. The
> properies for the last one were missing.
>
> Patch 2 adds a compatible string for the A83T USB PHY block.
>
> Patch 3 adds support for a secondary clock for the HSIC PHY. The
> HSIC block takes a 480MHz clock and a 12MHz clock. All known chips
> only have at most 1 HSIC capable host/PHY.
>
> Patch 4 adds support for the A83T's USB PHYs. The difference is
> mainly how the OTG PHY (PHY0) is configured.
>
> Patch 5 adds the device nodes for the USB PHY and hosts.
>
> Patch 6 adds the device node for the USB OTG controller.
>
> Patch 7 enables the USB hosts and peripherals on the Cubietruck Plus.
>
> Patch 8 enables the USB hosts and peripherals on the H8Homlet v2.
>
> The first four patches would go through linux-phy, while I will
> take the other four through the sunxi tree. For those who want
> to test this, the series is based on my previous "ARM: sun8i: a83t:
> Add support for MMC controllers v3" and "mfd: axp20x: Add basic
> support for AXP813 v2" series.
>
>
> Regards
> ChenYu
>
> Chen-Yu Tsai (8):
> dt-bindings: phy: sun4i-usb-phy: Add property descriptions for H3
> dt-bindings: phy: sun4i-usb-phy: Add compatible string for A83T
> phy: sun4i-usb: Support secondary clock for HSIC PHY
> phy: sun4i-usb: Support A83T USB PHYs
> ARM: sun8i: a83t: Add USB PHY and host device nodes
> ARM: sun8i: a83t: Add device node for USB OTG controller
> ARM: sun8i: a83t: cubietruck-plus: Enable onboard USB peripherals
> ARM: sun8i: a83t: h8homlet-v2: Enable USB ports
Applied the device tree patches.
ChenYu
^ permalink raw reply [flat|nested] 16+ messages in thread