From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chen-Yu Tsai Subject: Re: [PATCHv6 2/5] clk: socfpga: Add a clock type for the SD/MMC driver Date: Tue, 17 Dec 2013 10:17:26 +0800 Message-ID: References: <1386880245-10192-1-git-send-email-dinguyen@altera.com> <1386880245-10192-3-git-send-email-dinguyen@altera.com> <201312142233.27143.arnd@arndb.de> <52AD1185.6090501@linaro.org> <20131215045116.23538.4@quantum> <52AF68DB.7090105@elopez.com.ar> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <52AF68DB.7090105@elopez.com.ar> Sender: linux-mmc-owner@vger.kernel.org To: =?ISO-8859-1?Q?Emilio_L=F3pez?= Cc: Mike Turquette , zhangfei , Arnd Bergmann , dinguyen@altera.com, mark.rutland@arm.com, devicetree , dinh.linux@gmail.com, heiko@sntech.de, pawel.moll@arm.com, bzhao@marvell.com, tgih.jun@samsung.com, Peter De Schrijver , linux-mmc@vger.kernel.org, dianders@chromium.org, Rob Herring , jh80.chung@samsung.com, alim.akhtar@samsung.com, cjb@laptop.org, linux-arm-kernel , ian.campbell@citrix.com, Hans de Goede , =?ISO-8859-1?Q?David_Lanzend=F6rfer?= List-Id: devicetree@vger.kernel.org Hi, On Tue, Dec 17, 2013 at 4:55 AM, Emilio L=F3pez = wrote: > I also saw a similar requirement from the gmac people (on cc too), wh= o > needed to set the phy type (or something like that) on one of the clo= ck The GMAC clock register controls the tx clock source (a mux) and the interface type, which is most likely a gate to control the direction of the tx clock. So I modeled it as a composite clock source for now. I'm open to other options. > registers; so I'm thinking maybe a generic "tune something" approach = that > lets users configure some clock-dependent, arbitrary aspect of the cl= ock is > the way forward. Otherwise, we're going to end up bloating the clock > framework with a lot of callback pointers that are going to be used i= n one > or two clocks out of potentially hundreds on the whole system. ChenYu