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From: Chen-Yu Tsai <wens@kernel.org>
To: Michal Piekos <michal.piekos@mmpsystems.pl>
Cc: Daniel Lezcano <daniel.lezcano@kernel.org>,
	Thomas Gleixner <tglx@kernel.org>,  Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	 Jernej Skrabec <jernej.skrabec@gmail.com>,
	Samuel Holland <samuel@sholland.org>,
	 Maxime Ripard <mripard@kernel.org>,
	linux-kernel@vger.kernel.org,  devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	 linux-sunxi@lists.linux.dev,
	Andre Przywara <andre.przywara@arm.com>
Subject: Re: [PATCH v3 3/4] arm: dts: allwinner: t113s: add hstimer node
Date: Tue, 5 May 2026 22:39:59 +0800	[thread overview]
Message-ID: <CAGb2v67em9sO-R25hfH2_2WhD+cGfxEFQ6DeY9gobZoHdpRYdg@mail.gmail.com> (raw)
In-Reply-To: <20260428-h616-t113s-hstimer-v3-3-7e02178a93ee@mmpsystems.pl>

On Wed, Apr 29, 2026 at 12:29 AM Michal Piekos
<michal.piekos@mmpsystems.pl> wrote:
>
> Describe high speed timer block on Allwinner T113-S3.
>
> Tested on LCPI-PC-T113/F113:
> - hstimer is registered as clocksource
> - switching clocksource at runtime works
> - after rating increase hstimer operates as a broadcast clockevent device
>
> Signed-off-by: Michal Piekos <michal.piekos@mmpsystems.pl>
> ---
>  arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi
> index 424f4a2487e2..40e76cfc8a1d 100644
> --- a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi
> +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi
> @@ -34,6 +34,17 @@ cpu1: cpu@1 {
>                 };
>         };
>
> +       soc {
> +               hstimer@3008000 {
> +                       compatible = "allwinner,sun20i-d1-hstimer";
> +                       reg = <0x03008000 0x1000>;
> +                       interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_HSTIMER>;
> +                       resets = <&ccu RST_BUS_HSTIMER>;
> +               };
> +       };
> +

Actually this could probably be added to the common risc-v dtsi file instead:

    arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi

That way both the D1 and T113 / T113s benefit.

ChenYu

>         gic: interrupt-controller@1c81000 {
>                 compatible = "arm,gic-400";
>                 reg = <0x03021000 0x1000>,
>
> --
> 2.43.0
>
>

  parent reply	other threads:[~2026-05-05 14:40 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-28 16:26 [PATCH v3 0/4] Add hstimer support for H616 and T113-S3 Michal Piekos
2026-04-28 16:26 ` [PATCH v3 1/4] dt-bindings: timer: allwinner,sun5i-a13-hstimer: add H616 and D1 Michal Piekos
2026-04-28 16:26 ` [PATCH v3 2/4] clocksource/drivers/sun5i: add D1 hstimer support Michal Piekos
2026-05-05 14:32   ` Chen-Yu Tsai
2026-04-28 16:27 ` [PATCH v3 3/4] arm: dts: allwinner: t113s: add hstimer node Michal Piekos
2026-05-05 14:36   ` Chen-Yu Tsai
2026-05-05 14:39   ` Chen-Yu Tsai [this message]
2026-04-28 16:27 ` [PATCH v3 4/4] arm64: dts: allwinner: h616: " Michal Piekos
2026-05-05 14:34   ` Chen-Yu Tsai
2026-05-06 11:28 ` [PATCH v3 0/4] Add hstimer support for H616 and T113-S3 Daniel Lezcano
2026-05-06 14:41   ` Michal Piekos
2026-05-06 15:15     ` Daniel Lezcano

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