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AJvYcCXhWTQKyGq6mkOn/XhjOuvwhIUyX3FDGjE0ABiI4Ff7ys5gP3M7SSb5MeG68jSwZ4Var+7FIDUBFDzC@vger.kernel.org X-Gm-Message-State: AOJu0YwqmwkXqcQmqxXuhnoHo7IAVlr9yvAmEPP7Ivbfk/hx9uCGA7Cr qjlmNRF3lAmL1yC8ErZqqWGbepNBHZV/A4AIk5p7a/sfViPwLcLvBhtpKkbcpZepRKhAbaZJTGG N9D0p9lQvCh2AYuge92Zy52RwWRO+0oE= X-Gm-Gg: ASbGncsgul+pwtmnFS7kv5OXbYIGUMG95OQuuZZPKIHZE3848qnMzL12YQOOq0Dfp45 NW1rQbBj9FjVPiCAm6xzvTxyXIR2AMjz5wrKnoamD1h1wklagQy9QTS+XDD1Mx3GvbNENRInL1w Xoy4cslHGiCathZdD6JhmAkMHFUV9TcIs3Wnwvs4dXjdBcZz3BESLvQXK1RdHFVXwUa86ZVLpwv NvIZYLSx0goa112TYONEMQaRRxT/M5MRxjuCg4T X-Google-Smtp-Source: AGHT+IHjbRQmxK9nItl2HffExFNwVAi7q3n9PoNqjUew1CuTn1djxW2xNlMPlH1OQdzQN2XzFyIHcR/X/BEeXf1S/Xs= X-Received: by 2002:a17:90b:4d05:b0:329:e2b1:def3 with SMTP id 98e67ed59e1d1-339c271e913mr18582984a91.10.1759777295000; Mon, 06 Oct 2025 12:01:35 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250921083446.790374-1-uwu@icenowy.me> <20250921083446.790374-3-uwu@icenowy.me> <20250922204349.GA1290045-robh@kernel.org> <1ac8c72206abf9f3e0a13e1fcf44be5c605f6372.camel@icenowy.me> <36040a0a40311cb1e871075f0c5ad175342ed5db.camel@icenowy.me> <84566b33d0d08ad070c3aa8a01e07f3a0e3bff50.camel@icenowy.me> In-Reply-To: From: Christian Gmeiner Date: Mon, 6 Oct 2025 21:01:22 +0200 X-Gm-Features: AS18NWCjcsoivBsp8jaWAwEQpEhhNVJLV_pDpFJNQ8qKcsWUh9zL3A2T5EiSJg8 Message-ID: Subject: Re: [PATCH v2 2/8] dt-bindings: display: add verisilicon,dc To: Icenowy Zheng Cc: Rob Herring , Lucas Stach , Russell King , moderated for non-subscribers , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Krzysztof Kozlowski , Conor Dooley , Drew Fustini , Guo Ren , Fu Wei , Philipp Zabel , Heiko Stuebner , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Michal Wilczynski , Han Gao , Yao Zi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Am Mo., 6. Okt. 2025 um 18:34 Uhr schrieb Icenowy Zheng : > > =E5=9C=A8 2025-09-25=E6=98=9F=E6=9C=9F=E5=9B=9B=E7=9A=84 13:57 +0800=EF= =BC=8CIcenowy Zheng=E5=86=99=E9=81=93=EF=BC=9A > > =E5=9C=A8 2025-09-24=E6=98=9F=E6=9C=9F=E4=B8=89=E7=9A=84 20:15 +0200=EF= =BC=8CChristian Gmeiner=E5=86=99=E9=81=93=EF=BC=9A > > > > > > > Verisilicon has a series of display controllers prefixed > > > > > > > with > > > > > > > DC > > > > > > > and > > > > > > > with self-identification facility like their GC series > > > > > > > GPUs. > > > > > > > > > > > > > > Add a device tree binding for it. > > > > > > > > > > > > > > Depends on the specific DC model, it can have either one or > > > > > > > two > > > > > > > display > > > > > > > outputs, and each display output could be set to DPI signal > > > > > > > or > > > > > > > "DP" > > > > > > > signal (which seems to be some plain parallel bus to HDMI > > > > > > > controllers). > > > > > > > > > > > > > > Signed-off-by: Icenowy Zheng > > > > > > > --- > > > > > > > Changes in v2: > > > > > > > - Fixed misspelt "versilicon" in title. > > > > > > > - Moved minItems in clock properties to be earlier than > > > > > > > items. > > > > > > > - Re-aligned multi-line clocks and resets in example. > > > > > > > > > > > > > > .../bindings/display/verisilicon,dc.yaml | 127 > > > > > > > ++++++++++++++++++ > > > > > > > 1 file changed, 127 insertions(+) > > > > > > > create mode 100644 > > > > > > > Documentation/devicetree/bindings/display/verisilicon,dc.ya > > > > > > > ml > > > > > > > > > > > > > > diff --git > > > > > > > a/Documentation/devicetree/bindings/display/verisilicon,dc. > > > > > > > ya > > > > > > > ml > > > > > > > b/Documentation/devicetree/bindings/display/verisilicon,dc. > > > > > > > ya > > > > > > > ml > > > > > > > new file mode 100644 > > > > > > > index 0000000000000..07fedc4c7cc13 > > > > > > > --- /dev/null > > > > > > > +++ > > > > > > > b/Documentation/devicetree/bindings/display/verisilicon,dc. > > > > > > > ya > > > > > > > ml > > > > > > > @@ -0,0 +1,127 @@ > > > > > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > > > > > > +%YAML 1.2 > > > > > > > +--- > > > > > > > +$id: > > > > > > > http://devicetree.org/schemas/display/verisilicon,dc.yaml# > > > > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > > > > + > > > > > > > +title: Verisilicon DC-series display controllers > > > > > > > + > > > > > > > +maintainers: > > > > > > > + - Icenowy Zheng > > > > > > > + > > > > > > > +properties: > > > > > > > + $nodename: > > > > > > > + pattern: "^display@[0-9a-f]+$" > > > > > > > + > > > > > > > + compatible: > > > > > > > + const: verisilicon,dc > > > > > > > > > > > > This needs an SoC specific compatible. Generally licensed IP > > > > > > compatibles > > > > > > are useless because the specs aren't public and there's > > > > > > always > > > > > > integration quirks. > > > > > > > > > > This mimics the GPU IPs by the same vendor, see > > > > > gpu/vivante,gc.yaml , > > > > > which contain the exact same set of identification registers > > > > > (including > > > > > a "customer id" one that can differienate the same configured > > > > > IP > > > > > on > > > > > StarFive JH7110 and T-Head TH1520). > > > > > > > > > > If we can get vivante,gc to work w/o SoC specific compatible, > > > > > then we > > > > > should be able to get verisilicon,dc to work too. > > > > > > > > Well maybe I should add etnaviv people to the recipient list, to > > > > allow > > > > them to tell us the magic behind vivante,gc . > > > > > > > > > > Vivante GPUs are special because they contain registers that allow > > > them to > > > be fully identified - see etnaviv_hw_identify(..). > > > > > > We can read out the following information: > > > - model > > > - revision > > > - product_id > > > - customer_id > > > - eco_id > > > > Well Verisilicon DCs (sometimes also called Vivante DCs because > > Vivante > > is now part of Verisilicon) except DCNano have the same set of ID > > registers (In fact the registers before 0x1500 seem to have mostly > > the > > same meaning with GPUs, see [1], here the registers are even named > > GC{,REG}_xxx), so it's why I assume "verisilicon,dc" will work here. > > > > An example of identification registers readout on TH1510 is shown > > below: (the register names are from etnaviv state_hi.xml) > > ``` > > root@lpi4a66 [ ~ ] # busybox devmem 0xffef600020 # MODEL > > 0x00008200 > > root@lpi4a66 [ ~ ] # busybox devmem 0xffef600024 # REV > > 0x00005720 > > root@lpi4a66 [ ~ ] # busybox devmem 0xffef600028 # DATE > > 0x20210201 > > root@lpi4a66 [ ~ ] # busybox devmem 0xffef60002c # TIME > > 0x11133000 > > root@lpi4a66 [ ~ ] # busybox devmem 0xffef600030 # CUSTOMER_ID > > 0x0000030A > > root@lpi4a66 [ ~ ] # busybox devmem 0xffef6000a8 # PRODUCT_ID > > 0x02082000 > > root@lpi4a66 [ ~ ] # busybox devmem 0xffef6000e8 # ECO_ID > > 0x00000000 > > ``` > > > > Rob, > > Is this an acceptable answer of not having a vendor-specific > compatible? > > If it isn't, I will add vendor-specific compatible strings to the next > revision of the binding, and maybe also try to add them for vivante,gc. > There is no need to touch anything for vivante,gc. --=20 greets -- Christian Gmeiner, MSc https://christian-gmeiner.info/privacypolicy