From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B568C4332F for ; Thu, 3 Mar 2022 06:10:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229784AbiCCGKo (ORCPT ); Thu, 3 Mar 2022 01:10:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229468AbiCCGKn (ORCPT ); Thu, 3 Mar 2022 01:10:43 -0500 Received: from mail-oi1-x235.google.com (mail-oi1-x235.google.com [IPv6:2607:f8b0:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25F24165C02 for ; Wed, 2 Mar 2022 22:09:58 -0800 (PST) Received: by mail-oi1-x235.google.com with SMTP id 12so3883509oix.12 for ; Wed, 02 Mar 2022 22:09:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=F72bStix4IAs331NpnLfcvSkp3vRgdYM9D6jVxCO3QM=; b=mSmOEmxrWvorEYk7gtgGW3K4iwExNWCdjz0ETKAOYeEVbyg/cDPlngL2s7hEPx4/2P 1Dt9/loXa7MYg3XY39YIedYAdXyh2s6Hk4RCByvFFECGsnrOjiVGJm746faqn75T/tCI X8rLznuEa7mLlGd8AFgcWMzXYROccUbza3KAh4GXXEumgdBMSVHoGSMkl+kvg3mR0Ryh iEo8o0H/db4NyunEi7Jz2O4SqoTcpOG9Q/ZOkIdFY5ZtxwJqwEffbHD+weHSDd9jLpyr fps/FD6TN95wlMtVUiP7Xp+ghyc4DoM+drJSnhnp273OFM15OkQ1ydO4+BwAkJrpYO1R h+Gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=F72bStix4IAs331NpnLfcvSkp3vRgdYM9D6jVxCO3QM=; b=Ib6jGx1wSE44dI6GL5ha2VrNJofbb3YY9WwpjckMOVwtde53vUOIjxRU1cnF44EMQ9 tZAdf95Xy9a0+H6jjbNC2/y2llwHlUbe6anQb+a5yW6oXStK9V01ISSpcnfdrSsqcli/ 76pBkKqIQHXUas/02eHixppal2FtZan315Iq5tdPLl+CxmRk+T5tzjqIry5cevEqK+/k Ngy38S2GGg3imF1Ar63M9/QDbz6k8o3LaSDdgR1Z2L+6TyylNydrqujX3Ok7ak5K3nGi tlM4/05b459yoayjLYT/F7XxyUF0T1i8qsDflpk4zRHubDS7go7e1+8SLIdXs5m+ugYL uo8A== X-Gm-Message-State: AOAM531vkZqF1s4Lk53zRCt/CzhPQgGIqlbH1AvH93nDE5e1yYduPXFL wSVgtv02D3Vcj0M0m/eL3najKbPbvKgLkC4369NhYQ== X-Google-Smtp-Source: ABdhPJxP3AtADN5GNByKE/AGLTv6cQU/7GcPF7zfBmZLYqoxmlu3/BeupgEkWEqQsweRc3052c5+h2eBjUrfS2FL/lY= X-Received: by 2002:a54:4494:0:b0:2d7:652b:287 with SMTP id v20-20020a544494000000b002d7652b0287mr3236523oiv.126.1646287797432; Wed, 02 Mar 2022 22:09:57 -0800 (PST) MIME-Version: 1.0 References: <20220302203045.184500-1-bhupesh.sharma@linaro.org> <20220302203045.184500-8-bhupesh.sharma@linaro.org> In-Reply-To: From: Bhupesh Sharma Date: Thu, 3 Mar 2022 11:39:46 +0530 Message-ID: Subject: Re: [PATCH v3 7/7] arm64: dts: qcom: sa8155: Enable PCIe nodes To: Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, bhupesh.linux@gmail.com, lorenzo.pieralisi@arm.com, agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, linux-clk@vger.kernel.org, Vinod Koul Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Dmitry, On Thu, 3 Mar 2022 at 02:29, Dmitry Baryshkov wrote: > > On Wed, 2 Mar 2022 at 23:31, Bhupesh Sharma wrote: > > > > SA8155p ADP board supports the PCIe0 controller in the RC > > mode (only). So add the support for the same. > > > > Cc: Bjorn Andersson > > Cc: Vinod Koul > > Cc: Rob Herring > > Signed-off-by: Bhupesh Sharma > > --- > > arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 42 ++++++++++++++++++++++++ > > 1 file changed, 42 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts > > index 8756c2b25c7e..3f6b3ee404f5 100644 > > --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts > > +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts > > @@ -387,9 +387,51 @@ &usb_2_qmpphy { > > vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; > > }; > > > > +&pcie0 { > > + status = "okay"; > > +}; > > + > > +&pcie0_phy { > > + status = "okay"; > > + vdda-phy-supply = <&vreg_l18c_0p88>; > > + vdda-pll-supply = <&vreg_l8c_1p2>; > > +}; > > + > > +&pcie1_phy { > > + vdda-phy-supply = <&vreg_l18c_0p88>; > > + vdda-pll-supply = <&vreg_l8c_1p2>; > > +}; > > + > > &tlmm { > > gpio-reserved-ranges = <0 4>; > > > > + bt_en_default: bt_en_default { > > + mux { > > + pins = "gpio172"; > > + function = "gpio"; > > + }; > > + > > + config { > > + pins = "gpio172"; > > + drive-strength = <2>; > > + bias-pull-down; > > + }; > > + }; > > + > > + wlan_en_default: wlan_en_default { > > + mux { > > + pins = "gpio169"; > > + function = "gpio"; > > + }; > > + > > + config { > > + pins = "gpio169"; > > + drive-strength = <16>; > > + output-high; > > + bias-pull-up; > > + }; > > + }; > > + > > Not related to PCIe Hmm.. I have no strong personal opinion on this, so let's see what Bjorn thinks about the same. My reasoning for keeping it here was to just capture that we have 'bt_en' and 'wlan_en' related tlmm details here, so that when you send out the reworked QCAxxxx mfd series (see [1]) later, I can easily plug it in for SA8155p ADP dts as well with the 'bt' and 'wlan' constructs. [1]. https://lore.kernel.org/lkml/20210621223141.1638189-2-dmitry.baryshkov@linaro.org/T/ Regards. Bhupesh > > usb2phy_ac_en1_default: usb2phy_ac_en1_default { > > mux { > > pins = "gpio113"; > > -- > > 2.35.1 > > > > > -- > With best wishes > Dmitry