Re: [PATCH 04/12] dt-bindings: riscv: Add T-HEAD C920 compatibles

[Chen Wang <unicornxw@gmail.com>]

Thanks for your detailed clarification, Rob. I'll pay attention next time.
Regards,

unicornx

Rob Herring <robh@kernel.org> 于2023年9月15日周五 23:03写道：
>
> On Fri, Sep 15, 2023 at 03:11:43PM +0100, Conor Dooley wrote:
> > On Fri, Sep 15, 2023 at 03:23:33PM +0800, Wang Chen wrote:
> > > The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
> > > Notably, the C920 core is used in the SOPHGO SG2042 SoC.
> > >
> > > Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
> > > Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> >
> > I figure this is missing a From: or Co-developed-by line.
>
> From: (author) as 2 authors for 1 line change is questionable.
>
> The sender's email should be the last S-o-b. So like this:
>
> From: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
>
> ...
>
> Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
>
>
> >
> > > ---
> > >  Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > index 38c0b5213736..185a0191bad6 100644
> > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > @@ -47,6 +47,7 @@ properties:
> > >                - sifive,u74-mc
> > >                - thead,c906
> > >                - thead,c910
> > > +              - thead,c920
> > >            - const: riscv
> > >        - items:
> > >            - enum:
> > > --
> > > 2.25.1
> > >
>
>